git.libre-soc.org Git - soc.git/history - src/soc/experiment/sim.py

2020-07-22	Jacob Lifshay	Merge remote-tracking branch 'origin/master'	blob \| commitdiff \| raw
2020-07-22	Jacob Lifshay	format code	blob \| commitdiff \| raw
2020-07-12	Luke Kenneth Casso...	rename InternalOp to MicrOp	blob \| commitdiff \| raw \| diff to current
2020-04-17	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-04-11	Luke Kenneth Casso...	pass and lock immediate in	blob \| commitdiff \| raw \| diff to current
2020-04-11	Luke Kenneth Casso...	adding immediates, tracking down a bug	blob \| commitdiff \| raw \| diff to current
2020-04-10	Luke Kenneth Casso...	connect up ALU properly to pass full InternalOp subset...	blob \| commitdiff \| raw \| diff to current
2020-04-10	Luke Kenneth Casso...	eek, first cut at using POWER decoder2 in 6600 simulato...	blob \| commitdiff \| raw \| diff to current
2020-03-23	Luke Kenneth Casso...	split sim classes out into separate module	blob \| commitdiff \| raw \| diff to current