start putting state info into LoadStore1, slowly putting loadstore1.vhdl
[soc.git] / src / soc / fu / alu / alu_input_record.py
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-14 Luke Kenneth Casso... reduce code size by using CompOpSubsetBase for ALU...
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-05-31 Luke Kenneth Casso... remove commented-out vars from ALU input record
2020-05-31 Luke Kenneth Casso... add write_cr to ALU record subset
2020-05-21 Luke Kenneth Casso... comment CompALUOpSubset, data_len is actually used...
2020-05-21 Luke Kenneth Casso... add zero_a flag to CompALUOpSubset
2020-05-18 Luke Kenneth Casso... rename pipe to fu