too much debug info going past, so add the test registers to the
[soc.git] / src / soc / fu / div / pipe_data.py
2020-07-22 Jacob Lifshayworking on fsm
2020-07-18 Luke Kenneth Casso... worked out that DivPipeSpec can be given a default...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Jacob Lifshaystart adding FSMDivCore*
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Jacob Lifshayadd simulation-only division core using nmigen div...
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-10 Luke Kenneth Casso... propagate missing parameters from div
2020-07-09 Luke Kenneth Casso... create new DivMulOutputData which does not have CA...
2020-07-03 Luke Kenneth Casso... set only div/rem supported
2020-07-02 Luke Kenneth Casso... reduce DIV radix to 1
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-10 Jacob Lifshaycreate div pipe setup stage
2020-05-22 Luke Kenneth Casso... div probably uses ALU not Logical, needs double-checkin...
2020-05-22 Luke Kenneth Casso... cookie-cut start on div pipe