Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src / soc / fu / mmu /
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz'
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction...
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore...
2020-09-21 Luke Kenneth Casso... add missing file
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth Casso... do not need FAST regs in MMU
2020-09-15 Luke Kenneth Casso... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth Casso... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth Casso... use convenience vars
2020-09-15 Luke Kenneth Casso... add OP_TLBIE to mmu fsm
2020-09-15 Luke Kenneth Casso... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
2020-09-15 Luke Kenneth Casso... add MMU MTSPR connection into FSM
2020-09-15 Luke Kenneth Casso... add in MMU and DCache into MMU FSM
2020-09-15 Luke Kenneth Casso... add mmu fsm
2020-09-15 Luke Kenneth Casso... mmu uses RB, go with it
2020-09-15 Luke Kenneth Casso... add mmu initial pipe_data.py