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reduce sdram pins to smaller address and only 1 cs_n
[soc.git]
/
src
/
soc
/
litex
/
sim.py
2020-07-23
Luke Kenneth Casso...
try SDRAM SDR
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2020-07-23
Luke Kenneth Casso...
try different MEMTEST_xxx sizes with 64 bit bus width
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Luke Kenneth Casso...
re-add CRG (clock reset generator)
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2020-07-22
Luke Kenneth Casso...
add clock domain using snippet taken from random file
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2020-07-22
Luke Kenneth Casso...
update comments
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2020-07-22
Luke Kenneth Casso...
add boot-helper.S etc from microwatt litex core
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2020-07-22
Luke Kenneth Casso...
missed import of Builder, set cpu_type to "None" tempor...
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2020-07-22
Luke Kenneth Casso...
begin converting litex sim to libre-soc
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2020-07-22
Luke Kenneth Casso...
start from vexriscv sim.py from
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