add srcstep and correct PC-advancing during Sub-PC looping in ISACaller
[soc.git] / src / soc / simulator / qemu.py
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-12 Luke Kenneth Casso... attempting to get test_trap_sim working, seems to switc...
2020-07-11 Luke Kenneth Casso... sort out big/little endian startup on qemu
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-09 Luke Kenneth Casso... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... add option to qemu to break at known alternate address
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... fix qemu trap test
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... first cut at qemu memory dump and compare
2020-06-10 Michael Nolanmodify qemu.py to set qemu's cr to 0
2020-06-09 Luke Kenneth Casso... experimenting with CR/LR/XER etc in qemu
2020-06-09 Luke Kenneth Casso... add means to get pc and other qemu registers
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-15 Tobias Platenfix a bug in QemuController.get_register
2020-03-26 Luke Kenneth Casso... seeing spurious failures on gdb connection
2020-03-26 Luke Kenneth Casso... wait for communication with closing program and close...
2020-03-25 Michael NolanDirectly compare simulator with qemu
2020-03-25 Michael NolanAdd rudimentary python qemu interface