soc.git
3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Mon, 15 Feb 2021 16:19:15 +0000 (17:19 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agoShow traces for the register numbers of the current instruction
Cesar Strauss [Sun, 14 Feb 2021 22:49:02 +0000 (19:49 -0300)]
Show traces for the register numbers of the current instruction

Will make it easier to follow the vector loop, when it begins to increment
them.

3 years agoFix width of the "extra" input on the Extra decoder
Cesar Strauss [Sun, 14 Feb 2021 22:21:34 +0000 (19:21 -0300)]
Fix width of the "extra" input on the Extra decoder

The Extra field is nine bits long.

3 years agoFix conversion to MSB0
Cesar Strauss [Sun, 14 Feb 2021 21:47:02 +0000 (18:47 -0300)]
Fix conversion to MSB0

Correct formula is 31 - x.

3 years agoRemove obsolete comment
Cesar Strauss [Sun, 14 Feb 2021 19:16:24 +0000 (16:16 -0300)]
Remove obsolete comment

Forgot to remove the TODO item when I implemented it.

3 years agoadd comments to TestIssuer
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:25:56 +0000 (13:25 +0000)]
add comments to TestIssuer

3 years agoadd srcstep onto Vectorised GPRs in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:12:38 +0000 (13:12 +0000)]
add srcstep onto Vectorised GPRs in PowerDecoder2

3 years agoadd TestRunner comments
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:04:39 +0000 (13:04 +0000)]
add TestRunner comments

3 years agoadd Regfiles comments
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:03:13 +0000 (13:03 +0000)]
add Regfiles comments

3 years agoadd SVSTATE reading to TestIssuer
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:44:59 +0000 (12:44 +0000)]
add SVSTATE reading to TestIssuer

3 years agoadd SVSTATE to CoreState
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:37:45 +0000 (12:37 +0000)]
add SVSTATE to CoreState

3 years agoadd extra FSM explanatory comments to TestIssuer
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:34:38 +0000 (12:34 +0000)]
add extra FSM explanatory comments to TestIssuer

3 years agouse function for getting instruction from 32/64 bit fetch
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 22:53:22 +0000 (22:53 +0000)]
use function for getting instruction from 32/64 bit fetch

3 years agoFetch and decode the SVP64 prefix
Cesar Strauss [Sat, 13 Feb 2021 21:40:27 +0000 (18:40 -0300)]
Fetch and decode the SVP64 prefix

After fetching the word at the PC, send it combinatorially to the SVP64
decoder. Pass the decoded prefix (if any) to PowerDecoder2. If it's not a
prefix, hand over the instruction to the decoder. Otherwise, initiate a
read from the next memory location. Adjust the next instruction address
accordingly.

3 years agoOP_TLBIE must in be instr_is_priv
Tobias Platen [Sat, 13 Feb 2021 20:23:28 +0000 (21:23 +0100)]
OP_TLBIE must in be instr_is_priv

3 years agokeep commits to under 80 chars
Tobias Platen [Sat, 13 Feb 2021 20:13:50 +0000 (21:13 +0100)]
keep commits to under 80 chars

3 years agoCheck the PC value at the end of each instruction
Cesar Strauss [Sat, 13 Feb 2021 19:55:39 +0000 (16:55 -0300)]
Check the PC value at the end of each instruction

Useful for checking that the PC really points to the next instruction,
after fetching a prefixed instruction.

3 years agoSkip vector test case, and add a scalar case
Cesar Strauss [Sat, 13 Feb 2021 19:22:47 +0000 (16:22 -0300)]
Skip vector test case, and add a scalar case

Even if the prefix is a no-op, it will at least test the fetch unit.

3 years agoFix imports and whitespace
Cesar Strauss [Sat, 13 Feb 2021 18:59:17 +0000 (15:59 -0300)]
Fix imports and whitespace

3 years agoupdate svp64 unit test comments
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 18:29:06 +0000 (18:29 +0000)]
update svp64 unit test comments

3 years agoforward microwatt mmu specific SPR: PID and PRTBL
Tobias Platen [Sat, 13 Feb 2021 17:07:43 +0000 (18:07 +0100)]
forward microwatt mmu specific SPR: PID and PRTBL

3 years agoadd SVP64 TestIssuer separate unit test
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 12:27:08 +0000 (12:27 +0000)]
add SVP64 TestIssuer separate unit test

3 years agosplit out TestRunner into separate module
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 12:23:50 +0000 (12:23 +0000)]
split out TestRunner into separate module

3 years agoFix SVP64 translator to yield the unaltered instruction
Cesar Strauss [Sat, 13 Feb 2021 09:12:09 +0000 (06:12 -0300)]
Fix SVP64 translator to yield the unaltered instruction

Being a generator, it yields one item at a time, instead of appending to
a list.
Clean up the now unused return list, and simplify the iterator.

3 years agoadd one SVP64 ALU test case to get started
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:23:44 +0000 (15:23 +0000)]
add one SVP64 ALU test case to get started

3 years agoadd SVSTATE to TestCase infrastructure for use in TestIssuer
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:23:05 +0000 (15:23 +0000)]
add SVSTATE to TestCase infrastructure for use in TestIssuer

3 years agoadd skip of instruction if SVSTATE.VL=0 in ISACaller
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:07:09 +0000 (15:07 +0000)]
add skip of instruction if SVSTATE.VL=0 in ISACaller

3 years agovalidate all registers to make sure no damage occurs in SVP64 ISACaller
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:02:43 +0000 (15:02 +0000)]
validate all registers to make sure no damage occurs in SVP64 ISACaller

3 years agoadd srcstep and correct PC-advancing during Sub-PC looping in ISACaller
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 14:41:48 +0000 (14:41 +0000)]
add srcstep and correct PC-advancing during Sub-PC looping in ISACaller

3 years agocomments
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 13:20:02 +0000 (13:20 +0000)]
comments

3 years agoadd in SVSTATE.srcstep update, loop from 0 to VL-1
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 13:18:16 +0000 (13:18 +0000)]
add in SVSTATE.srcstep update, loop from 0 to VL-1

3 years agoallow PC to update by 8 in SVP64 mode
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 13:06:49 +0000 (13:06 +0000)]
allow PC to update by 8 in SVP64 mode

3 years agofix setting of SVSTATE.VL and MVL
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 12:55:01 +0000 (12:55 +0000)]
fix setting of SVSTATE.VL and MVL

3 years agoadd in SVSTATE to ISACaller, not used, just passed in
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 12:51:21 +0000 (12:51 +0000)]
add in SVSTATE to ISACaller, not used, just passed in

3 years agocomments in TestIssuer for SVP64PrefixDecoder
Luke Kenneth Casson Leighton [Thu, 11 Feb 2021 15:57:25 +0000 (15:57 +0000)]
comments in TestIssuer for SVP64PrefixDecoder

3 years agoadd svp64 reg decode detection to ISACaller output
Luke Kenneth Casson Leighton [Wed, 10 Feb 2021 15:25:06 +0000 (15:25 +0000)]
add svp64 reg decode detection to ISACaller output

3 years agostarting to add SVP64 register EXTRA-read and isvec to ISACaller
Luke Kenneth Casson Leighton [Tue, 9 Feb 2021 19:46:02 +0000 (19:46 +0000)]
starting to add SVP64 register EXTRA-read and isvec to ISACaller

3 years agocomment update
Luke Kenneth Casson Leighton [Thu, 4 Feb 2021 16:53:53 +0000 (16:53 +0000)]
comment update

3 years agoadd missing newline at end of experiment/formal/.gitignore
colepoirier [Tue, 9 Feb 2021 22:38:47 +0000 (14:38 -0800)]
add missing newline at end of experiment/formal/.gitignore

3 years agofix erroneous removal of proof* from experiment/formal/.gitignore, now
colepoirier [Tue, 9 Feb 2021 22:36:31 +0000 (14:36 -0800)]
fix erroneous removal of proof* from experiment/formal/.gitignore, now
proof*/**

3 years agoadd skeleton implementation of experiment/formal/proof_icache.py to
colepoirier [Sun, 7 Feb 2021 22:33:43 +0000 (14:33 -0800)]
add skeleton implementation of experiment/formal/proof_icache.py to
so I can solicit help

3 years agoicache.py fix formatting
colepoirier [Sun, 7 Feb 2021 22:33:14 +0000 (14:33 -0800)]
icache.py fix formatting

3 years agoModify experiment/formal/.gitignore because was preventing commiting
colepoirier [Sun, 7 Feb 2021 22:30:16 +0000 (14:30 -0800)]
Modify experiment/formal/.gitignore because was preventing commiting
proof_icache.py

3 years agoFix whitespace
Cesar Strauss [Sat, 6 Feb 2021 21:33:26 +0000 (18:33 -0300)]
Fix whitespace

3 years agoExtract the fetch FSM out from the main FSM
Cesar Strauss [Sat, 6 Feb 2021 20:53:22 +0000 (17:53 -0300)]
Extract the fetch FSM out from the main FSM

Allows future extension to prefixed instructions, as well as being an
opportunity for pipeline optimization.

At start, the fetch FSM waits for the PC to be stable. This
happens when there is no longer an instruction being executed.
When done, it hands over the instruction to the decoder.

3 years agofix hanging simulation
Tobias Platen [Fri, 5 Feb 2021 20:01:08 +0000 (21:01 +0100)]
fix hanging simulation

3 years agosrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
Tobias Platen [Thu, 4 Feb 2021 20:01:38 +0000 (21:01 +0100)]
src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave

3 years agoupdate test_issuer_mmu_data_path.py to handle SPRs
Tobias Platen [Thu, 4 Feb 2021 19:26:51 +0000 (20:26 +0100)]
update test_issuer_mmu_data_path.py to handle SPRs

3 years agopass SPR MicroOp to MMU function unit
Tobias Platen [Thu, 4 Feb 2021 19:19:39 +0000 (20:19 +0100)]
pass SPR MicroOp to MMU function unit

3 years agonope - need it to be zero if not identified as svp64
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:26:15 +0000 (21:26 +0000)]
nope - need it to be zero if not identified as svp64

3 years agoactually no need to mux in the svp64_rm, just the id "is this svp64" is enough
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:24:05 +0000 (21:24 +0000)]
actually no need to mux in the svp64_rm, just the id "is this svp64" is enough

3 years agoadd SVP64PowerDecoder, extracts svp64 remap if correctly identified
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:23:22 +0000 (21:23 +0000)]
add SVP64PowerDecoder, extracts svp64 remap if correctly identified

3 years agoISACaller, in svp64 mode, read the next 32 bits when SVP64 identified
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 21:23:22 +0000 (21:23 +0000)]
ISACaller, in svp64 mode, read the next 32 bits when SVP64 identified

3 years agoextending the GTKWave document in test_issuer when microwatt_mmu = True
Tobias Platen [Mon, 1 Feb 2021 20:07:53 +0000 (21:07 +0100)]
extending the GTKWave document in test_issuer when microwatt_mmu = True

3 years agosort out SelectableInt bit-ordering for identifying SVP64 fields
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 14:49:01 +0000 (14:49 +0000)]
sort out SelectableInt bit-ordering for identifying SVP64 fields

3 years agoconstruct the assembly-code prefix and base v3.0B in SVP64Asm class
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 14:21:49 +0000 (14:21 +0000)]
construct the assembly-code prefix and base v3.0B in SVP64Asm class

3 years agoAdd GTKWave document to test_issuer
Cesar Strauss [Mon, 1 Feb 2021 09:43:36 +0000 (06:43 -0300)]
Add GTKWave document to test_issuer

3 years agoFix loop test and enable it
Cesar Strauss [Sun, 31 Jan 2021 20:18:18 +0000 (17:18 -0300)]
Fix loop test and enable it

Make the code correspond to the comments and vice-versa.
Due to the branching, this test is useful for ensuring correctness of the
interaction between instruction fetch and issue.

3 years agostart an ISACaller SVP64 unit test
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:42:29 +0000 (20:42 +0000)]
start an ISACaller SVP64 unit test

3 years agotest SVP64 major opcode, start checking if it is EXT001 soon
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:28:27 +0000 (20:28 +0000)]
test SVP64 major opcode, start checking if it is EXT001 soon

3 years agoadjusting ISACaller unit test to use ISACaller.setup_one()
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:04:10 +0000 (20:04 +0000)]
adjusting ISACaller unit test to use ISACaller.setup_one()

3 years agofix ISACaller unit test
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 19:51:27 +0000 (19:51 +0000)]
fix ISACaller unit test

3 years agofix two syntax errors in src/soc/decoder/isa/caller.py
Tobias Platen [Sun, 31 Jan 2021 18:48:18 +0000 (19:48 +0100)]
fix two syntax errors in src/soc/decoder/isa/caller.py

3 years agoSVP64 Remap Fields structures for ISACaller
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 18:03:01 +0000 (18:03 +0000)]
SVP64 Remap Fields structures for ISACaller

3 years agoremove sv_rm from PowerDecoder register decoders
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 16:01:16 +0000 (16:01 +0000)]
remove sv_rm from PowerDecoder register decoders

3 years agoadd SVSTATE SPR sub-field accessor class to ISACaller
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:53:19 +0000 (15:53 +0000)]
add SVSTATE SPR sub-field accessor class to ISACaller

3 years agomove SVP64 Extra reg decoding into main PowerDecoder module
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:28:02 +0000 (15:28 +0000)]
move SVP64 Extra reg decoding into main PowerDecoder module

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:08:29 +0000 (15:08 +0000)]
update submodule

3 years agomove CR in/out SVP64 EXTRA decoders into PowerDecoder
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 17:53:21 +0000 (17:53 +0000)]
move CR in/out SVP64 EXTRA decoders into PowerDecoder
this due to satellite SubsetPowerDecoders containing unnecessary SVP64decoders

3 years agoadd SVP64 CR out extending to 7-bit in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 14:04:02 +0000 (14:04 +0000)]
add SVP64 CR out extending to 7-bit in PowerDecoder2

3 years agoadd SVP64 CR EXTRA field-extension, from 3-bit to 7-bit (plus isvec)
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:55:55 +0000 (13:55 +0000)]
add SVP64 CR EXTRA field-extension, from 3-bit to 7-bit (plus isvec)
in PowerDecoder2

3 years agoextend CR registers in Decode2ToExecute1Type to 7 bit
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:17:45 +0000 (13:17 +0000)]
extend CR registers in Decode2ToExecute1Type to 7 bit

3 years agoadd SVP64CRExtra class to PowerDecoder2, turns 3-bit CR into 7-bit plus isvec
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:10:16 +0000 (13:10 +0000)]
add SVP64CRExtra class to PowerDecoder2, turns 3-bit CR into 7-bit plus isvec

3 years agosplit out SVEXTRA field selection/decoding into separate class SVP64ExtraSpec
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:55:21 +0000 (12:55 +0000)]
split out SVEXTRA field selection/decoding into separate class SVP64ExtraSpec
in PowerDecoder2

3 years agowhoops update PowerDecoder2 svp64 comments, reg sizes (7 bit)
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:46:38 +0000 (12:46 +0000)]
whoops update PowerDecoder2 svp64 comments, reg sizes (7 bit)

3 years agoadd SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:36:22 +0000 (00:36 +0000)]
add SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
DecodeOut2 will have to wait because it is more complex

3 years agoadd first SVP64 7-bit register context decoder to PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:17:20 +0000 (00:17 +0000)]
add first SVP64 7-bit register context decoder to PowerDecoder2

3 years agoadd SVP64RM record to PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:01:06 +0000 (23:01 +0000)]
add SVP64RM record to PowerDecoder2

3 years agoincrease register number sizes from 5 to 7
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:00:46 +0000 (23:00 +0000)]
increase register number sizes from 5 to 7

3 years agosyntax corrections, also size of maxvl was wrong
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:51:37 +0000 (22:51 +0000)]
syntax corrections, also size of maxvl was wrong

3 years agoadd SVP64 RM (Remap) Record
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:46:43 +0000 (22:46 +0000)]
add SVP64 RM (Remap) Record

3 years agoadjust SVP64RM class to output more PowerDecoder-friendly csv augmentation
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:39:44 +0000 (22:39 +0000)]
adjust SVP64RM class to output more PowerDecoder-friendly csv augmentation
add SVEXTRA power_enum
extend PowerDecoder fields (sv in/out regs)

3 years agoadjust how register copy/setup is done in PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 18:42:08 +0000 (18:42 +0000)]
adjust how register copy/setup is done in PowerDecoder2

3 years agoadd SV etype/ptype to power decoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 14:59:49 +0000 (14:59 +0000)]
add SV etype/ptype to power decoder

3 years agowhoops syntax error. submodule update
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 12:12:12 +0000 (12:12 +0000)]
whoops syntax error.  submodule update

3 years agostart adding svp64 enums
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:56:35 +0000 (11:56 +0000)]
start adding svp64 enums

3 years agouse new svp64-augmented csv reader in PowerDecoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:33:22 +0000 (11:33 +0000)]
use new svp64-augmented csv reader in PowerDecoder

3 years agowhoops missed out "+" on explicit license listing
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:19:14 +0000 (11:19 +0000)]
whoops missed out "+" on explicit license listing

3 years agoadd SVSTATE to StateRegs
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 16:07:29 +0000 (16:07 +0000)]
add SVSTATE to StateRegs
(also fix comments)

3 years agoadd SVState SPR Record, SVSTATERec
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 15:53:50 +0000 (15:53 +0000)]
add SVState SPR Record, SVSTATERec

3 years agoadd svp64 CR field identification for EXTRA2/3 decoding
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:38:34 +0000 (18:38 +0000)]
add svp64 CR field identification for EXTRA2/3 decoding

3 years agomove svp64 reg-decode function to more appropriate location
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:16:47 +0000 (18:16 +0000)]
move svp64 reg-decode function to more appropriate location
use it in SVP64RM get_svp64_csv to decode EXTRA bit-field positions

3 years agoprovide "merger" of SVP64 RM info into v3.0B CSV files
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:49:05 +0000 (12:49 +0000)]
provide "merger" of SVP64 RM info into v3.0B CSV files

3 years agouse SPR constants
Tobias Platen [Wed, 27 Jan 2021 19:45:37 +0000 (20:45 +0100)]
use SPR constants

3 years agomove SVP64RM CSV class to new module
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:38:35 +0000 (12:38 +0000)]
move SVP64RM CSV class to new module

3 years agowhitespace and shortening of SPR MMU redirection in Power Decoder
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:35:30 +0000 (12:35 +0000)]
whitespace and shortening of SPR MMU redirection in Power Decoder

3 years agoalso read LDST RM files
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:25:40 +0000 (12:25 +0000)]
also read LDST RM files

3 years ago[Bug 580] update comment above changed block
Tobias Platen [Tue, 26 Jan 2021 19:37:41 +0000 (20:37 +0100)]
[Bug 580] update comment above changed block

3 years ago[Bug 580] redirect MMU SPRs to the MMU
Tobias Platen [Tue, 26 Jan 2021 19:27:40 +0000 (20:27 +0100)]
[Bug 580] redirect MMU SPRs to the MMU

3 years agoextra comments in svp64
Luke Kenneth Casson Leighton [Mon, 25 Jan 2021 16:23:07 +0000 (16:23 +0000)]
extra comments in svp64