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arg complete rewrite of JTAG2DMI, based it on staf (chips4makers) WB
2020-09-21 Luke Kenneth Casson... arg complete rewrite of JTAG2DMI, based it on staf...
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2020-09-20 Luke Kenneth Casson... resolve issues in async sim: must not drive async clock...
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2020-09-20 Luke Kenneth Casson... still experimenting with async FF sync
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2020-09-20 Luke Kenneth Casson... continuing async clock experimenting
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2020-09-20 Luke Kenneth Casson... add an async clock synchronizer experiment
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2020-09-20 Luke Kenneth Casson... first version code-morph on dmi2jtag
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2020-09-19 Luke Kenneth Casson... add pc_o not connected
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2020-09-19 Luke Kenneth Casson... set ROM to empty, set SRAM to tiny 0x200, get things...
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2020-09-19 Luke Kenneth Casson... urk. wishbone slave devices declared incorrectly (I...
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2020-09-19 Luke Kenneth Casson... disable internal RAM set SRAM to much smaller
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2020-09-19 Luke Kenneth Casson... shrink size of SRAM to 8k, move things around
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2020-09-19 Luke Kenneth Casson... add (disabled) tri-state GPIO
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2020-09-19 Luke Kenneth Casson... remove the gpio peripheral which was previously hard...
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2020-09-19 Luke Kenneth Casson... add 3x EINTs to ls180soc
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2020-09-18 Luke Kenneth Casson... add SPI, sdcard, preliminary GPIO to ls180 pinouts
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2020-09-18 Luke Kenneth Casson... argh got fed up trying to shoe-horn into sim.py
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2020-09-18 Luke Kenneth Casson... can remove unneeded overrides of Prev/Next Control
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2020-09-17 Luke Kenneth Casson... add versa ecp5 fpga litex build script
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2020-09-16 Luke Kenneth Casson... make a start on LS180 platform
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2020-09-15 Luke Kenneth Casson... add back (totally confusing) accidentally-removed code...
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2020-09-15 Luke Kenneth Casson... instantiate MMU from AllFunctionUnits
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2020-09-15 Luke Kenneth Casson... do not need FAST regs in MMU
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2020-09-15 Luke Kenneth Casson... comment mmu test
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2020-09-15 Luke Kenneth Casson... add edge-triggering to dcache/mmu "valid"
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2020-09-15 Luke Kenneth Casson... add set MTSPR prtbl to mmu unit test
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2020-09-15 Luke Kenneth Casson... add OP_MFSPR to mmu
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2020-09-15 Luke Kenneth Casson... use convenience vars
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2020-09-15 Luke Kenneth Casson... add OP_TLBIE to mmu fsm
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2020-09-15 Luke Kenneth Casson... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
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2020-09-15 Luke Kenneth Casson... add MMU MTSPR connection into FSM
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2020-09-15 Luke Kenneth Casson... add in MMU and DCache into MMU FSM
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2020-09-15 Luke Kenneth Casson... moved PLRU to nmutil
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2020-09-15 Luke Kenneth Casson... add mmu fsm
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2020-09-15 Luke Kenneth Casson... remove more (confusing/spurious) types, should be in...
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2020-09-15 Luke Kenneth Casson... remove more (confusing/spurious) types, should be in...
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2020-09-15 Luke Kenneth Casson... remove more (confusing/spurious) types, should be in...
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2020-09-15 Luke Kenneth Casson... removed (confusing/spurious) types, should be in .pyi...
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2020-09-15 Luke Kenneth Casson... add MMU FunctionUnit
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2020-09-15 Luke Kenneth Casson... mmu uses RB, go with it
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2020-09-15 Luke Kenneth Casson... add OP_TLBIE
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2020-09-15 Luke Kenneth Casson... add mmu initial pipe_data.py
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2020-09-15 Luke Kenneth Casson... add extra "modes" to PortInterface
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2020-09-15 Luke Kenneth Casson... syntax error correction
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2020-09-15 Luke Kenneth Casson... add inline comments into icache.py
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2020-09-14 Luke Kenneth Casson... increase TLB_NUM_WAYS to 4
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2020-09-14 Luke Kenneth Casson... vhdl conversion not really working for plru
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2020-09-14 Luke Kenneth Casson... add array signal names
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2020-09-14 Luke Kenneth Casson... rename plru input
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2020-09-14 Luke Kenneth Casson... rename plru input
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2020-09-14 Luke Kenneth Casson... reorg mmu lookup test so it is called twice
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2020-09-14 Luke Kenneth Casson... TLB PLRUs are of TLB_WAY_BITS width
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2020-09-14 Luke Kenneth Casson... fix mmu perms/lookup in dcache
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2020-09-14 Luke Kenneth Casson... whitespace
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2020-09-14 Luke Kenneth Casson... remove duplicated signal
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2020-09-14 Luke Kenneth Casson... comments on icache
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2020-09-14 Luke Kenneth Casson... get rid of rst
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2020-09-14 Luke Kenneth Casson... use word_select
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2020-09-14 Luke Kenneth Casson... add mmu-dcache test
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2020-09-13 Luke Kenneth Casson... dcache truncate wishbone address, store real_addr in...
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2020-09-13 Luke Kenneth Casson... last mmu get seems ok
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2020-09-13 Luke Kenneth Casson... whoops recursion error v.shift calculated from v.shift
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2020-09-13 Luke Kenneth Casson... more experimenting with mmu READ_WAIT state
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2020-09-13 Luke Kenneth Casson... radix tree wait error, investigating
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2020-09-13 Luke Kenneth Casson... mmu test starting to make sense
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2020-09-13 Luke Kenneth Casson... floundering around with MMU unit test, no idea what...
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2020-09-13 Luke Kenneth Casson... mmu code-morph
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2020-09-13 Luke Kenneth Casson... code-morph, add masked function
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2020-09-13 Luke Kenneth Casson... move code to mmu_0
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2020-09-13 Luke Kenneth Casson... add example radix walk from power-gem5
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2020-09-13 Luke Kenneth Casson... MMU test
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2020-09-13 Luke Kenneth Casson... submodule update
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2020-09-13 Luke Kenneth Casson... clarify
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2020-09-13 Luke Kenneth Casson... sort out ariane PLRU, rename/clarify
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2020-09-13 Luke Kenneth Casson... minor error in plru
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2020-09-13 Luke Kenneth Casson... rename cache_valid_bits to cache_validsg
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2020-09-13 Luke Kenneth Casson... cache_valid_idx too large in dcache
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2020-09-13 Luke Kenneth Casson... whoops, cache valid array too small in dcache
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2020-09-12 Luke Kenneth Casson... more dcache debugging
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2020-09-12 Luke Kenneth Casson... missing reservation address comparison
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2020-09-12 Luke Kenneth Casson... dcache tidyup
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2020-09-12 Luke Kenneth Casson... more dcache debugging
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2020-09-12 Luke Kenneth Casson... add random dcache mem test
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2020-09-12 Luke Kenneth Casson... cache valid corrupted: fixed
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2020-09-12 Luke Kenneth Casson... adding names to array signals
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2020-09-12 Luke Kenneth Casson... whoops, indentation error
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2020-09-12 Luke Kenneth Casson... enable Display debugs
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2020-09-12 Luke Kenneth Casson... set bytesel in dcache store
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2020-09-11 Luke Kenneth Casson... separat stbs_done into ld/st
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2020-09-11 Luke Kenneth Casson... dcache load/store test
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2020-09-11 Luke Kenneth Casson... debugging dcache
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2020-09-11 Luke Kenneth Casson... wrong width for data / addr
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2020-09-11 Luke Kenneth Casson... connect up WB SRAM to dcache test
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2020-09-11 Luke Kenneth Casson... start on dcache test
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2020-09-11 Luke Kenneth Casson... missing comb +=
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2020-09-11 Luke Kenneth Casson... missing maybe_tlb_plrus
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2020-09-11 Luke Kenneth Casson... WAY_BITS not TLB_WAY_BITS
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2020-09-11 Luke Kenneth Casson... whoops new node not to be calculated at end
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2020-09-11 Luke Kenneth Casson... try to get better DTLBUpdate
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2020-09-11 Luke Kenneth Casson... simplify dcache pending
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2020-09-11 Luke Kenneth Casson... move dcache pending test to separate module
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