bit more on TRAP handling (preparing priv instruction)
[soc.git] / src / soc / fu / trap /
drwxr-xr-x   ..
-rw-r--r-- 8558 main_stage.py
-rw-r--r-- 1174 pipe_data.py
drwxr-xr-x - test
-rw-r--r-- 1370 trap_input_data.py