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[soclayout.git] / experiments12 / memory.py

diff --git a/experiments12/memory.py b/experiments12/memory.py
index 81782dd1aa75f6d4a770166869072ef7399e0efb..565d179ec20c196dcf9c2ed65b69f27bf7fb2dcc 100644 (file)
--- a/experiments12/memory.py
+++ b/experiments12/memory.py
@@ -1,9 +1,10 @@
-from nmigen import Elaboratable, Cat, Module, Signal, Instance
+from nmigen import Elaboratable, Cat, Module, Signal, ClockSignal, Instance
 from nmigen.cli import rtlil
 
 
 class ADD(Elaboratable):
     def __init__(self, width):
+        self.we  = Signal(8)
         self.a   = Signal(width)
         self.b   = Signal(width)
         self.f   = Signal(width)
@@ -17,8 +18,8 @@ class ADD(Elaboratable):
         a = Signal(9)
         q = Signal(64) # output
         d = Signal(64) # input
-        we = Signal(8)
-        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
+        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
+                                             i_we=self.we, i_clk=ClockSignal())
         m.submodules += sram
 
         # connect up some arbitrary signals
@@ -35,5 +36,5 @@ def create_ilang(dut, ports, test_name):
         f.write(vl)
 
 if __name__ == "__main__":
-    alu = ADD(width=4)
-    create_ilang(alu, [alu.a, alu.b, alu.f], "memory")
+    alu = ADD(width=64)
+    create_ilang(alu, [alu.a, alu.b, alu.f, alu.we], "memory")