Uodated doDesign for the latest ls180 (sram variant).

[soclayout.git] / experiments9 / tsmc_c018 / coriolis2 / settings.py

diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py
index 1142e7a8c16c37b9cb223c2c8832b00c178aab53..c3aac12110ff66d266455004c2b2fcdb8a610f66 100644 (file)
--- a/experiments9/tsmc_c018/coriolis2/settings.py
+++ b/experiments9/tsmc_c018/coriolis2/settings.py
@@ -29,8 +29,8 @@ LibreSOCMem.setup()
 
 with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.misc.catchCore           = False
-    cfg.misc.minTraceLevel       = 14700
-    cfg.misc.maxTraceLevel       = 14800
+    cfg.misc.minTraceLevel       = 12300
+    cfg.misc.maxTraceLevel       = 12400
     cfg.misc.info                = False
     cfg.misc.paranoid            = False
     cfg.misc.bug                 = False