git.libre-soc.org Git - soclayout.git/history - experiments9/tsmc

2021-04-12	Luke Kenneth Casso...	update PLL signal output names	blob \| commitdiff \| raw
2021-04-09	Luke Kenneth Casso...	whitespace	blob \| commitdiff \| raw \| diff to current
2021-04-09	Luke Kenneth Casso...	whitespace cleanup	blob \| commitdiff \| raw \| diff to current
2021-03-29	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	blob \| commitdiff \| raw \| diff to current
2021-03-29	Jean-Paul Chaput	Add a placeholder for the PLL in the doDesign.py for...	blob \| commitdiff \| raw \| diff to current
2021-03-23	Jean-Paul Chaput	Uodated doDesign for the latest ls180 (sram variant).	blob \| commitdiff \| raw \| diff to current
2021-03-14	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	blob \| commitdiff \| raw \| diff to current
2021-03-14	Jean-Paul Chaput	Adjusted doDesign.py scripts to use Chip.doChipFloorplan().	blob \| commitdiff \| raw \| diff to current
2021-03-09	Jean-Paul Chaput	First working version of the Flexlib + P&R flow for...	blob \| commitdiff \| raw \| diff to current
2021-03-05	Jean-Paul Chaput	Added support files for ls180+SRAM on TSMC 180nm.	blob \| commitdiff \| raw \| diff to current