1 # generate add.il ilang file with: python3 add.py
4 from nmigen
import Elaboratable
, Signal
, Module
5 from nmigen
.cli
import rtlil
8 # clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
9 # $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
10 # for each: $ python3 setup.py develop --user
12 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
15 class ADD(Elaboratable
):
16 def __init__(self
, width
):
17 self
.a
= Signal(width
)
18 self
.b
= Signal(width
)
19 self
.f
= Signal(width
)
20 self
.io_in
= Signal(1)
21 self
.io_out
= Signal(1)
24 self
.jtag
= TAP(ir_width
=3)
25 self
.jtag
.bus
.tck
.name
= 'tck'
26 self
.jtag
.bus
.tms
.name
= 'tms'
27 self
.jtag
.bus
.tdo
.name
= 'tdo'
28 self
.jtag
.bus
.tdi
.name
= 'tdi'
30 # have to create at least one shift register
31 self
.sr
= self
.jtag
.add_shiftreg(ircode
=4, length
=3)
34 self
.ios
= self
.jtag
.add_io(name
="test", iotype
=IOType
.In
)
36 def elaborate(self
, platform
):
38 m
.d
.comb
+= self
.io_in
.eq(False)
39 m
.d
.comb
+= self
.io_out
.eq(True)
41 m
.submodules
.jtag
= jtag
= self
.jtag
42 m
.d
.comb
+= self
.sr
.i
.eq(self
.sr
.o
) # loopback test
45 m
.d
.sync
+= self
.f
.eq(self
.a
+ self
.b
)
50 def create_ilang(dut
, ports
, test_name
):
51 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
52 with
open("%s.il" % test_name
, "w") as f
:
55 if __name__
== "__main__":
57 create_ilang(alu
, [alu
.a
, alu
.b
, alu
.f
,
58 alu
.io_in
, alu
.io_out
,
62 alu
.jtag
.bus
.tdi
], "add")