3 # full core build including QTY 4of 4k SRAMs: please remember to alter
4 # doDesign.py before running!
5 # change the settings to the larger chip/corona size
7 # also contains Staf's manually re-connected PLL edits to the verilog
8 # see commits 24cbbcc and 227a0f69
10 echo "remember to check doDesign core size"
11 echo "also use yosys 049e3abf9"
13 # initialise/update the pinmux submodule
14 git submodule update
--init --remote
16 # makes symlinks to alliance
19 # generates the io pads needed for ioring.py
24 rm *.vst
*.ap
*.blif
*.gds
26 # copies over a "full" core
27 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il
28 cp non_generated
/full_core_4_4ksram_ls180.v ls180.v
29 cp non_generated
/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
30 cp non_generated
/full_core_4_4ksram_libresoc_recon.v libresoc.v
31 cp non_generated
/spblock
*.v .
32 cp non_generated
/spblock
*.vbe .
33 cp non_generated
/pll.v .
41 # make the vst from verilog