src/soc/config/test/test_fetch.py

   1 from soc.minerva.units.fetch import FetchUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.ifetch import ConfigFetchUnit
   7 from collections import namedtuple
   8 from nmigen.cli import rtlil
   9
  10 from soc.config.test.test_loadstore import TestMemPspec
  11
  12 import sys
  13 sys.setrecursionlimit(10**6)
  14
  15
  16 def read_from_addr(dut, addr):
  17     yield dut.a_pc_i.eq(addr)
  18     yield dut.a_i_valid.eq(1)
  19     yield dut.f_i_valid.eq(1)
  20     yield dut.a_stall_i.eq(1)
  21     yield
  22     yield dut.a_stall_i.eq(0)
  23     yield
  24     yield Settle()
  25     while (yield dut.f_busy_o):
  26         yield
  27     res = (yield dut.f_instr_o)
  28
  29     yield dut.a_i_valid.eq(0)
  30     yield dut.f_i_valid.eq(0)
  31     yield
  32     return res
  33
  34
  35 def tst_lsmemtype(ifacetype, sram_depth=32):
  36     m = Module()
  37     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
  38                          imem_ifacetype=ifacetype, addr_wid=64,
  39                          mask_wid=4,
  40                          reg_wid=32,
  41                          imem_test_depth=sram_depth)
  42     dut = ConfigFetchUnit(pspec).fu
  43     vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
  44     with open("test_fetch_%s.il" % ifacetype, "w") as f:
  45         f.write(vl)
  46
  47     m.submodules.dut = dut
  48
  49     sim = Simulator(m)
  50     sim.add_clock(1e-6)
  51
  52     mem = dut._get_memory()
  53
  54     def process():
  55
  56         values = [random.randint(0, (1 << 32)-1) for x in range(16)]
  57         for addr, val in enumerate(values):
  58             yield mem._array[addr].eq(val)
  59         yield Settle()
  60
  61         for addr, val in enumerate(values):
  62             x = yield from read_from_addr(dut, addr << 2)
  63             print("addr, val", addr, hex(val), hex(x))
  64             assert x == val
  65
  66     sim.add_sync_process(process)
  67     with sim.write_vcd("test_fetch_%s.vcd" % ifacetype, traces=[]):
  68         sim.run()
  69
  70
  71 if __name__ == '__main__':
  72     tst_lsmemtype('test_bare_wb', sram_depth=32768)
  73     tst_lsmemtype('testmem')