src/soc/config/test/test_fetch.py

   1 from soc.minerva.units.fetch import FetchUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.ifetch import ConfigFetchUnit
   7 from collections import namedtuple
   8 from nmigen.cli import rtlil
   9
  10 from soc.config.test.test_loadstore import TestMemPspec
  11
  12 import sys
  13 sys.setrecursionlimit(10**6)
  14
  15
  16 def read_from_addr(dut, addr, stall=True):
  17     yield dut.a_pc_i.eq(addr)
  18     yield dut.a_i_valid.eq(1)
  19     yield dut.f_i_valid.eq(1)
  20     if stall:
  21         yield dut.a_stall_i.eq(1)
  22         yield
  23         yield dut.a_stall_i.eq(0)
  24     yield
  25     yield Settle()
  26     while (yield dut.f_busy_o):
  27         yield
  28     res = (yield dut.f_instr_o)
  29
  30     yield dut.a_i_valid.eq(0)
  31     yield dut.f_i_valid.eq(0)
  32     yield
  33     return res
  34
  35
  36 def tst_lsmemtype(ifacetype, sram_depth=32):
  37     m = Module()
  38     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
  39                          imem_ifacetype=ifacetype, addr_wid=64,
  40                          mask_wid=4,
  41                          reg_wid=32,
  42                          imem_test_depth=sram_depth)
  43     dut = ConfigFetchUnit(pspec).fu
  44     vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
  45     with open("test_fetch_%s.il" % ifacetype, "w") as f:
  46         f.write(vl)
  47
  48     m.submodules.dut = dut
  49
  50     sim = Simulator(m)
  51     sim.add_clock(1e-6)
  52
  53     mem = dut._get_memory()
  54
  55     def process():
  56
  57         values = [random.randint(0, (1 << 32)-1) for x in range(16)]
  58         for addr, val in enumerate(values):
  59             yield mem._array[addr].eq(val)
  60         yield Settle()
  61
  62         for addr, val in enumerate(values):
  63             x = yield from read_from_addr(dut, addr << 2)
  64             print("addr, val", addr, hex(val), hex(x))
  65             assert x == val
  66
  67     sim.add_sync_process(process)
  68     with sim.write_vcd("test_fetch_%s.vcd" % ifacetype, traces=[]):
  69         sim.run()
  70
  71
  72 if __name__ == '__main__':
  73     tst_lsmemtype('test_bare_wb', sram_depth=32768)
  74     tst_lsmemtype('testmem')