3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
6 from nmigen
import (Module
, Signal
, Elaboratable
, Const
)
7 from nmigen
.cli
import rtlil
8 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
10 from nmigen_soc
.wishbone
.sram
import SRAM
11 from nmigen
import Memory
, Signal
, Module
13 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
, Tick
14 from nmutil
.util
import wrap
15 from nmigen_soc
.wishbone
import Interface
as WishboneInterface
18 # JTAG to DMI interface
23 # req : ____/------------\_____
27 # din : xxxxxxxxxxxx< >xxx
28 # ack : ____________/------\___
30 # * addr/dout set along with req, can be latched on same cycle by slave
31 # * ack & din remain up until req is dropped by master, the slave must
32 # provide a stable output on din on reads during that time.
33 # * req remains low at until at least one sysclk after ack seen down.
38 def external_ports(self
):
39 return [self
.bus
.tdo
, self
.bus
.tdi
, self
.bus
.tms
, self
.bus
.tck
]
42 if __name__
== '__main__':
43 dut
= DMITAP(ir_width
=4)
44 iotypes
= (IOType
.In
, IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
)
45 ios
= [dut
.add_io(iotype
=iotype
) for iotype
in iotypes
]
46 dut
.sr
= dut
.add_shiftreg(ircode
=4, length
=3) # test loopback register
48 # create and connect wishbone SRAM (a quick way to do WB test)
49 dut
.wb
= dut
.add_wishbone(ircodes
=[5, 6, 7], features
={'err'},
50 address_width
=16, data_width
=16)
52 # create DMI2JTAG (goes through to dmi_sim())
53 dut
.dmi
= dut
.add_dmi(ircodes
=[8, 9, 10])
55 vl
= rtlil
.convert(dut
)
56 with
open("test_dmi2jtag.il", "w") as f
: