src/soc/decoder/isa/caller.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020 Michael Nolan
   4 # Funded by NLnet http://nlnet.nl
   5 """core of the python-based POWER9 simulator
   6
   7 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   8 not speed, it is for both learning and educational purposes, as well as
   9 a method of verifying the HDL.
  10
  11 related bugs:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  14 """
  15
  16 from nmigen.back.pysim import Settle
  17 from functools import wraps
  18 from copy import copy
  19 from soc.decoder.orderedset import OrderedSet
  20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  21                                         selectconcat)
  22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  23                                      insns, MicrOp, In1Sel, In2Sel, In3Sel,
  24                                      OutSel, CROutSel)
  25
  26 from soc.decoder.power_enums import SVPtype
  27
  28 from soc.decoder.helpers import exts, gtu, ltu, undefined
  29 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  30 from soc.decoder.power_svp64 import SVP64RM, decode_extra
  31
  32 from soc.decoder.isa.radixmmu import RADIX
  33 from soc.decoder.isa.mem import Mem, swap_order
  34
  35 from collections import namedtuple
  36 import math
  37 import sys
  38
  39 instruction_info = namedtuple('instruction_info',
  40                               'func read_regs uninit_regs write_regs ' +
  41                               'special_regs op_fields form asmregs')
  42
  43 special_sprs = {
  44     'LR': 8,
  45     'CTR': 9,
  46     'TAR': 815,
  47     'XER': 1,
  48     'VRSAVE': 256}
  49
  50
  51 REG_SORT_ORDER = {
  52     # TODO (lkcl): adjust other registers that should be in a particular order
  53     # probably CA, CA32, and CR
  54     "RT": 0,
  55     "RA": 0,
  56     "RB": 0,
  57     "RS": 0,
  58     "CR": 0,
  59     "LR": 0,
  60     "CTR": 0,
  61     "TAR": 0,
  62     "CA": 0,
  63     "CA32": 0,
  64     "MSR": 0,
  65     "SVSTATE": 0,
  66
  67     "overflow": 1,
  68 }
  69
  70
  71 def create_args(reglist, extra=None):
  72     retval = list(OrderedSet(reglist))
  73     retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
  74     if extra is not None:
  75         return [extra] + retval
  76     return retval
  77
  78
  79
  80 class GPR(dict):
  81     def __init__(self, decoder, isacaller, svstate, regfile):
  82         dict.__init__(self)
  83         self.sd = decoder
  84         self.isacaller = isacaller
  85         self.svstate = svstate
  86         for i in range(32):
  87             self[i] = SelectableInt(regfile[i], 64)
  88
  89     def __call__(self, ridx):
  90         return self[ridx]
  91
  92     def set_form(self, form):
  93         self.form = form
  94
  95     def getz(self, rnum):
  96         # rnum = rnum.value # only SelectableInt allowed
  97         print("GPR getzero?", rnum)
  98         if rnum == 0:
  99             return SelectableInt(0, 64)
 100         return self[rnum]
 101
 102     def _get_regnum(self, attr):
 103         getform = self.sd.sigforms[self.form]
 104         rnum = getattr(getform, attr)
 105         return rnum
 106
 107     def ___getitem__(self, attr):
 108         """ XXX currently not used
 109         """
 110         rnum = self._get_regnum(attr)
 111         offs = self.svstate.srcstep
 112         print("GPR getitem", attr, rnum, "srcoffs", offs)
 113         return self.regfile[rnum]
 114
 115     def dump(self):
 116         for i in range(0, len(self), 8):
 117             s = []
 118             for j in range(8):
 119                 s.append("%08x" % self[i+j].value)
 120             s = ' '.join(s)
 121             print("reg", "%2d" % i, s)
 122
 123
 124 class PC:
 125     def __init__(self, pc_init=0):
 126         self.CIA = SelectableInt(pc_init, 64)
 127         self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
 128
 129     def update_nia(self, is_svp64):
 130         increment = 8 if is_svp64 else 4
 131         self.NIA = self.CIA + SelectableInt(increment, 64)
 132
 133     def update(self, namespace, is_svp64):
 134         """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
 135         """
 136         self.CIA = namespace['NIA'].narrow(64)
 137         self.update_nia(is_svp64)
 138         namespace['CIA'] = self.CIA
 139         namespace['NIA'] = self.NIA
 140
 141
 142 # Simple-V: see https://libre-soc.org/openpower/sv
 143 class SVP64State:
 144     def __init__(self, init=0):
 145         self.spr = SelectableInt(init, 32)
 146         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
 147         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
 148         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
 149         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
 150         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
 151         self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
 152         self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
 153
 154
 155 # SVP64 ReMap field
 156 class SVP64RMFields:
 157     def __init__(self, init=0):
 158         self.spr = SelectableInt(init, 24)
 159         # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
 160         self.mmode = FieldSelectableInt(self.spr, [0])
 161         self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
 162         self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
 163         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
 164         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
 165         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
 166         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 167         # these cover the same extra field, split into parts as EXTRA2
 168         self.extra2 = list(range(4))
 169         self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
 170         self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
 171         self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
 172         self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
 173         self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
 174         # and here as well, but EXTRA3
 175         self.extra3 = list(range(3))
 176         self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
 177         self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
 178         self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
 179
 180
 181 SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
 182 SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
 183 SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
 184 SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
 185 SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
 186 SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
 187 SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
 188 SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
 189 SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
 190
 191
 192 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
 193 class SVP64PrefixFields:
 194     def __init__(self):
 195         self.insn = SelectableInt(0, 32)
 196         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
 197         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
 198         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
 199         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
 200         self.rm = FieldSelectableInt(self.insn, rmfields)
 201
 202
 203 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
 204 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
 205 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
 206
 207
 208 class SPR(dict):
 209     def __init__(self, dec2, initial_sprs={}):
 210         self.sd = dec2
 211         dict.__init__(self)
 212         for key, v in initial_sprs.items():
 213             if isinstance(key, SelectableInt):
 214                 key = key.value
 215             key = special_sprs.get(key, key)
 216             if isinstance(key, int):
 217                 info = spr_dict[key]
 218             else:
 219                 info = spr_byname[key]
 220             if not isinstance(v, SelectableInt):
 221                 v = SelectableInt(v, info.length)
 222             self[key] = v
 223
 224     def __getitem__(self, key):
 225         print("get spr", key)
 226         print("dict", self.items())
 227         # if key in special_sprs get the special spr, otherwise return key
 228         if isinstance(key, SelectableInt):
 229             key = key.value
 230         if isinstance(key, int):
 231             key = spr_dict[key].SPR
 232         key = special_sprs.get(key, key)
 233         if key == 'HSRR0':  # HACK!
 234             key = 'SRR0'
 235         if key == 'HSRR1':  # HACK!
 236             key = 'SRR1'
 237         if key in self:
 238             res = dict.__getitem__(self, key)
 239         else:
 240             if isinstance(key, int):
 241                 info = spr_dict[key]
 242             else:
 243                 info = spr_byname[key]
 244             dict.__setitem__(self, key, SelectableInt(0, info.length))
 245             res = dict.__getitem__(self, key)
 246         print("spr returning", key, res)
 247         return res
 248
 249     def __setitem__(self, key, value):
 250         if isinstance(key, SelectableInt):
 251             key = key.value
 252         if isinstance(key, int):
 253             key = spr_dict[key].SPR
 254             print("spr key", key)
 255         key = special_sprs.get(key, key)
 256         if key == 'HSRR0':  # HACK!
 257             self.__setitem__('SRR0', value)
 258         if key == 'HSRR1':  # HACK!
 259             self.__setitem__('SRR1', value)
 260         print("setting spr", key, value)
 261         dict.__setitem__(self, key, value)
 262
 263     def __call__(self, ridx):
 264         return self[ridx]
 265
 266 def get_pdecode_idx_in(dec2, name):
 267     op = dec2.dec.op
 268     in1_sel = yield op.in1_sel
 269     in2_sel = yield op.in2_sel
 270     in3_sel = yield op.in3_sel
 271     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 272     in1 = yield dec2.e.read_reg1.data
 273     in2 = yield dec2.e.read_reg2.data
 274     in3 = yield dec2.e.read_reg3.data
 275     in1_isvec = yield dec2.in1_isvec
 276     in2_isvec = yield dec2.in2_isvec
 277     in3_isvec = yield dec2.in3_isvec
 278     print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
 279                                      in1, in1_isvec)
 280     print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
 281                                      in2, in2_isvec)
 282     print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
 283                                      in3, in3_isvec)
 284     # identify which regnames map to in1/2/3
 285     if name == 'RA':
 286         if (in1_sel == In1Sel.RA.value or
 287             (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
 288             return in1, in1_isvec
 289         if in1_sel == In1Sel.RA_OR_ZERO.value:
 290             return in1, in1_isvec
 291     elif name == 'RB':
 292         if in2_sel == In2Sel.RB.value:
 293             return in2, in2_isvec
 294         if in3_sel == In3Sel.RB.value:
 295             return in3, in3_isvec
 296     # XXX TODO, RC doesn't exist yet!
 297     elif name == 'RC':
 298         assert False, "RC does not exist yet"
 299     elif name == 'RS':
 300         if in1_sel == In1Sel.RS.value:
 301             return in1, in1_isvec
 302         if in2_sel == In2Sel.RS.value:
 303             return in2, in2_isvec
 304         if in3_sel == In3Sel.RS.value:
 305             return in3, in3_isvec
 306     return None, False
 307
 308
 309 def get_pdecode_cr_out(dec2, name):
 310     op = dec2.dec.op
 311     out_sel = yield op.cr_out
 312     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
 313     sv_cr_out = yield op.sv_cr_out
 314     spec = yield dec2.crout_svdec.spec
 315     sv_override = yield dec2.dec_cr_out.sv_override
 316     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 317     out = yield dec2.e.write_cr.data
 318     o_isvec = yield dec2.o_isvec
 319     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
 320     print ("    sv_cr_out", sv_cr_out)
 321     print ("    cr_bf", out_bitfield)
 322     print ("    spec", spec)
 323     print ("    override", sv_override)
 324     # identify which regnames map to out / o2
 325     if name == 'CR0':
 326         if out_sel == CROutSel.CR0.value:
 327             return out, o_isvec
 328     print ("get_pdecode_idx_out not found", name)
 329     return None, False
 330
 331
 332 def get_pdecode_idx_out(dec2, name):
 333     op = dec2.dec.op
 334     out_sel = yield op.out_sel
 335     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 336     out = yield dec2.e.write_reg.data
 337     o_isvec = yield dec2.o_isvec
 338     # identify which regnames map to out / o2
 339     if name == 'RA':
 340         print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
 341         if out_sel == OutSel.RA.value:
 342             return out, o_isvec
 343     elif name == 'RT':
 344         print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
 345                                       OutSel.RT_OR_ZERO.value, out, o_isvec)
 346         if out_sel == OutSel.RT.value:
 347             return out, o_isvec
 348     print ("get_pdecode_idx_out not found", name)
 349     return None, False
 350
 351
 352 # XXX TODO
 353 def get_pdecode_idx_out2(dec2, name):
 354     op = dec2.dec.op
 355     print ("TODO: get_pdecode_idx_out2", name)
 356     return None, False
 357
 358
 359 class ISACaller:
 360     # decoder2 - an instance of power_decoder2
 361     # regfile - a list of initial values for the registers
 362     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 363     # respect_pc - tracks the program counter.  requires initial_insns
 364     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 365                  initial_mem=None, initial_msr=0,
 366                  initial_svstate=0,
 367                  initial_insns=None, respect_pc=False,
 368                  disassembly=None,
 369                  initial_pc=0,
 370                  bigendian=False,
 371                  mmu=False):
 372
 373         self.bigendian = bigendian
 374         self.halted = False
 375         self.is_svp64_mode = False
 376         self.respect_pc = respect_pc
 377         if initial_sprs is None:
 378             initial_sprs = {}
 379         if initial_mem is None:
 380             initial_mem = {}
 381         if initial_insns is None:
 382             initial_insns = {}
 383             assert self.respect_pc == False, "instructions required to honor pc"
 384
 385         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 386         print("ISACaller initial_msr", initial_msr)
 387
 388         # "fake program counter" mode (for unit testing)
 389         self.fake_pc = 0
 390         disasm_start = 0
 391         if not respect_pc:
 392             if isinstance(initial_mem, tuple):
 393                 self.fake_pc = initial_mem[0]
 394                 disasm_start = self.fake_pc
 395         else:
 396             disasm_start = initial_pc
 397
 398         # disassembly: we need this for now (not given from the decoder)
 399         self.disassembly = {}
 400         if disassembly:
 401             for i, code in enumerate(disassembly):
 402                 self.disassembly[i*4 + disasm_start] = code
 403
 404         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 405         self.svp64rm = SVP64RM()
 406         if isinstance(initial_svstate, int):
 407             initial_svstate = SVP64State(initial_svstate)
 408         self.svstate = initial_svstate
 409         self.gpr = GPR(decoder2, self, self.svstate, regfile)
 410         self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
 411         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 412         if mmu:
 413             self.mem = RADIX(self.mem, self)
 414         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 415         self.pc = PC()
 416         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 417
 418         # TODO, needed here:
 419         # FPR (same as GPR except for FP nums)
 420         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 421         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 422         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 423         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 424         #         -- Done
 425         # 2.3.2 LR   (actually SPR #8) -- Done
 426         # 2.3.3 CTR  (actually SPR #9) -- Done
 427         # 2.3.4 TAR  (actually SPR #815)
 428         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 429         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 430
 431         # create CR then allow portions of it to be "selectable" (below)
 432         #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
 433         self.cr = SelectableInt(initial_cr, 64)  # underlying reg
 434         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 435
 436         # "undefined", just set to variable-bit-width int (use exts "max")
 437         #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 438
 439         self.namespace = {}
 440         self.namespace.update(self.spr)
 441         self.namespace.update({'GPR': self.gpr,
 442                                'MEM': self.mem,
 443                                'SPR': self.spr,
 444                                'memassign': self.memassign,
 445                                'NIA': self.pc.NIA,
 446                                'CIA': self.pc.CIA,
 447                                'SVSTATE': self.svstate.spr,
 448                                'CR': self.cr,
 449                                'MSR': self.msr,
 450                                'undefined': undefined,
 451                                'mode_is_64bit': True,
 452                                'SO': XER_bits['SO']
 453                                })
 454
 455         # update pc to requested start point
 456         self.set_pc(initial_pc)
 457
 458         # field-selectable versions of Condition Register TODO check bitranges?
 459         self.crl = []
 460         for i in range(8):
 461             bits = tuple(range(i*4+32, (i+1)*4+32))  # errr... maybe?
 462             _cr = FieldSelectableInt(self.cr, bits)
 463             self.crl.append(_cr)
 464             self.namespace["CR%d" % i] = _cr
 465
 466         self.decoder = decoder2.dec
 467         self.dec2 = decoder2
 468
 469     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 470         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 471         # store CIA(+4?) in SRR0, set NIA to 0x700
 472         # store MSR in SRR1, set MSR to um errr something, have to check spec
 473         self.spr['SRR0'].value = self.pc.CIA.value
 474         self.spr['SRR1'].value = self.namespace['MSR'].value
 475         self.trap_nia = SelectableInt(trap_addr, 64)
 476         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 477
 478         # set exception bits.  TODO: this should, based on the address
 479         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 480         # bits appropriately.  however it turns out that *for now* in all
 481         # cases (all trap_addrs) the exact same thing is needed.
 482         self.msr[MSRb.IR] = 0
 483         self.msr[MSRb.DR] = 0
 484         self.msr[MSRb.FE0] = 0
 485         self.msr[MSRb.FE1] = 0
 486         self.msr[MSRb.EE] = 0
 487         self.msr[MSRb.RI] = 0
 488         self.msr[MSRb.SF] = 1
 489         self.msr[MSRb.TM] = 0
 490         self.msr[MSRb.VEC] = 0
 491         self.msr[MSRb.VSX] = 0
 492         self.msr[MSRb.PR] = 0
 493         self.msr[MSRb.FP] = 0
 494         self.msr[MSRb.PMM] = 0
 495         self.msr[MSRb.TEs] = 0
 496         self.msr[MSRb.TEe] = 0
 497         self.msr[MSRb.UND] = 0
 498         self.msr[MSRb.LE] = 1
 499
 500     def memassign(self, ea, sz, val):
 501         self.mem.memassign(ea, sz, val)
 502
 503     def prep_namespace(self, formname, op_fields):
 504         # TODO: get field names from form in decoder*1* (not decoder2)
 505         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 506         # from spec
 507         # then "yield" fields only from op_fields rather than hard-coded
 508         # list, here.
 509         fields = self.decoder.sigforms[formname]
 510         for name in op_fields:
 511             if name == 'spr':
 512                 sig = getattr(fields, name.upper())
 513             else:
 514                 sig = getattr(fields, name)
 515             val = yield sig
 516             # these are all opcode fields involved in index-selection of CR,
 517             # and need to do "standard" arithmetic.  CR[BA+32] for example
 518             # would, if using SelectableInt, only be 5-bit.
 519             if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
 520                 self.namespace[name] = val
 521             else:
 522                 self.namespace[name] = SelectableInt(val, sig.width)
 523
 524         self.namespace['XER'] = self.spr['XER']
 525         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 526         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 527
 528     def handle_carry_(self, inputs, outputs, already_done):
 529         inv_a = yield self.dec2.e.do.invert_in
 530         if inv_a:
 531             inputs[0] = ~inputs[0]
 532
 533         imm_ok = yield self.dec2.e.do.imm_data.ok
 534         if imm_ok:
 535             imm = yield self.dec2.e.do.imm_data.data
 536             inputs.append(SelectableInt(imm, 64))
 537         assert len(outputs) >= 1
 538         print("outputs", repr(outputs))
 539         if isinstance(outputs, list) or isinstance(outputs, tuple):
 540             output = outputs[0]
 541         else:
 542             output = outputs
 543         gts = []
 544         for x in inputs:
 545             print("gt input", x, output)
 546             gt = (gtu(x, output))
 547             gts.append(gt)
 548         print(gts)
 549         cy = 1 if any(gts) else 0
 550         print("CA", cy, gts)
 551         if not (1 & already_done):
 552             self.spr['XER'][XER_bits['CA']] = cy
 553
 554         print("inputs", already_done, inputs)
 555         # 32 bit carry
 556         # ARGH... different for OP_ADD... *sigh*...
 557         op = yield self.dec2.e.do.insn_type
 558         if op == MicrOp.OP_ADD.value:
 559             res32 = (output.value & (1 << 32)) != 0
 560             a32 = (inputs[0].value & (1 << 32)) != 0
 561             if len(inputs) >= 2:
 562                 b32 = (inputs[1].value & (1 << 32)) != 0
 563             else:
 564                 b32 = False
 565             cy32 = res32 ^ a32 ^ b32
 566             print("CA32 ADD", cy32)
 567         else:
 568             gts = []
 569             for x in inputs:
 570                 print("input", x, output)
 571                 print("     x[32:64]", x, x[32:64])
 572                 print("     o[32:64]", output, output[32:64])
 573                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 574                 gts.append(gt)
 575             cy32 = 1 if any(gts) else 0
 576             print("CA32", cy32, gts)
 577         if not (2 & already_done):
 578             self.spr['XER'][XER_bits['CA32']] = cy32
 579
 580     def handle_overflow(self, inputs, outputs, div_overflow):
 581         if hasattr(self.dec2.e.do, "invert_in"):
 582             inv_a = yield self.dec2.e.do.invert_in
 583             if inv_a:
 584                 inputs[0] = ~inputs[0]
 585
 586         imm_ok = yield self.dec2.e.do.imm_data.ok
 587         if imm_ok:
 588             imm = yield self.dec2.e.do.imm_data.data
 589             inputs.append(SelectableInt(imm, 64))
 590         assert len(outputs) >= 1
 591         print("handle_overflow", inputs, outputs, div_overflow)
 592         if len(inputs) < 2 and div_overflow is None:
 593             return
 594
 595         # div overflow is different: it's returned by the pseudo-code
 596         # because it's more complex than can be done by analysing the output
 597         if div_overflow is not None:
 598             ov, ov32 = div_overflow, div_overflow
 599         # arithmetic overflow can be done by analysing the input and output
 600         elif len(inputs) >= 2:
 601             output = outputs[0]
 602
 603             # OV (64-bit)
 604             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 605             output_sgn = exts(output.value, output.bits) < 0
 606             ov = 1 if input_sgn[0] == input_sgn[1] and \
 607                 output_sgn != input_sgn[0] else 0
 608
 609             # OV (32-bit)
 610             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 611             output32_sgn = exts(output.value, 32) < 0
 612             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 613                 output32_sgn != input32_sgn[0] else 0
 614
 615         self.spr['XER'][XER_bits['OV']] = ov
 616         self.spr['XER'][XER_bits['OV32']] = ov32
 617         so = self.spr['XER'][XER_bits['SO']]
 618         so = so | ov
 619         self.spr['XER'][XER_bits['SO']] = so
 620
 621     def handle_comparison(self, outputs, cr_idx=0):
 622         out = outputs[0]
 623         assert isinstance(out, SelectableInt), \
 624             "out zero not a SelectableInt %s" % repr(outputs)
 625         print("handle_comparison", out.bits, hex(out.value))
 626         # TODO - XXX *processor* in 32-bit mode
 627         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 628         # if is_32bit:
 629         #    o32 = exts(out.value, 32)
 630         #    print ("handle_comparison exts 32 bit", hex(o32))
 631         out = exts(out.value, out.bits)
 632         print("handle_comparison exts", hex(out))
 633         zero = SelectableInt(out == 0, 1)
 634         positive = SelectableInt(out > 0, 1)
 635         negative = SelectableInt(out < 0, 1)
 636         SO = self.spr['XER'][XER_bits['SO']]
 637         print("handle_comparison SO", SO)
 638         cr_field = selectconcat(negative, positive, zero, SO)
 639         self.crl[cr_idx].eq(cr_field)
 640
 641     def set_pc(self, pc_val):
 642         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 643         self.pc.update(self.namespace, self.is_svp64_mode)
 644
 645     def setup_one(self):
 646         """set up one instruction
 647         """
 648         if self.respect_pc:
 649             pc = self.pc.CIA.value
 650         else:
 651             pc = self.fake_pc
 652         self._pc = pc
 653         ins = self.imem.ld(pc, 4, False, True)
 654         if ins is None:
 655             raise KeyError("no instruction at 0x%x" % pc)
 656         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 657         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 658
 659         yield self.dec2.sv_rm.eq(0)
 660         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 661         yield self.dec2.dec.bigendian.eq(self.bigendian)
 662         yield self.dec2.state.msr.eq(self.msr.value)
 663         yield self.dec2.state.pc.eq(pc)
 664         if self.svstate is not None:
 665             yield self.dec2.state.svstate.eq(self.svstate.spr.value)
 666
 667         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
 668         yield Settle()
 669         opcode = yield self.dec2.dec.opcode_in
 670         pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
 671         pfx.insn.value = opcode
 672         major = pfx.major.asint(msb0=True) # MSB0 inversion
 673         print ("prefix test: opcode:", major, bin(major),
 674                 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
 675         self.is_svp64_mode = ((major == 0b000001) and
 676                               pfx.insn[7].value == 0b1 and
 677                               pfx.insn[9].value == 0b1)
 678         self.pc.update_nia(self.is_svp64_mode)
 679         self.namespace['NIA'] = self.pc.NIA
 680         self.namespace['SVSTATE'] = self.svstate.spr
 681         if not self.is_svp64_mode:
 682             return
 683
 684         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
 685         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 686         print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
 687         print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
 688         sv_rm = pfx.rm.asint(msb0=True)
 689         ins = self.imem.ld(pc+4, 4, False, True)
 690         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
 691         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
 692         yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix
 693         yield Settle()
 694
 695     def execute_one(self):
 696         """execute one instruction
 697         """
 698         # get the disassembly code for this instruction
 699         if self.is_svp64_mode:
 700             code = self.disassembly[self._pc+4]
 701             print("    svp64 sim-execute", hex(self._pc), code)
 702         else:
 703             code = self.disassembly[self._pc]
 704             print("sim-execute", hex(self._pc), code)
 705         opname = code.split(' ')[0]
 706         yield from self.call(opname)
 707
 708         # don't use this except in special circumstances
 709         if not self.respect_pc:
 710             self.fake_pc += 4
 711
 712         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 713
 714     def get_assembly_name(self):
 715         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 716         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 717         dec_insn = yield self.dec2.e.do.insn
 718         asmcode = yield self.dec2.dec.op.asmcode
 719         print("get assembly name asmcode", asmcode, hex(dec_insn))
 720         asmop = insns.get(asmcode, None)
 721         int_op = yield self.dec2.dec.op.internal_op
 722
 723         # sigh reconstruct the assembly instruction name
 724         if hasattr(self.dec2.e.do, "oe"):
 725             ov_en = yield self.dec2.e.do.oe.oe
 726             ov_ok = yield self.dec2.e.do.oe.ok
 727         else:
 728             ov_en = False
 729             ov_ok = False
 730         if hasattr(self.dec2.e.do, "rc"):
 731             rc_en = yield self.dec2.e.do.rc.rc
 732             rc_ok = yield self.dec2.e.do.rc.ok
 733         else:
 734             rc_en = False
 735             rc_ok = False
 736         # grrrr have to special-case MUL op (see DecodeOE)
 737         print("ov %d en %d rc %d en %d op %d" %
 738               (ov_ok, ov_en, rc_ok, rc_en, int_op))
 739         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 740             print("mul op")
 741             if rc_en & rc_ok:
 742                 asmop += "."
 743         else:
 744             if not asmop.endswith("."):  # don't add "." to "andis."
 745                 if rc_en & rc_ok:
 746                     asmop += "."
 747         if hasattr(self.dec2.e.do, "lk"):
 748             lk = yield self.dec2.e.do.lk
 749             if lk:
 750                 asmop += "l"
 751         print("int_op", int_op)
 752         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 753             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 754             print("AA", AA)
 755             if AA:
 756                 asmop += "a"
 757         spr_msb = yield from self.get_spr_msb()
 758         if int_op == MicrOp.OP_MFCR.value:
 759             if spr_msb:
 760                 asmop = 'mfocrf'
 761             else:
 762                 asmop = 'mfcr'
 763         # XXX TODO: for whatever weird reason this doesn't work
 764         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 765         if int_op == MicrOp.OP_MTCRF.value:
 766             if spr_msb:
 767                 asmop = 'mtocrf'
 768             else:
 769                 asmop = 'mtcrf'
 770         return asmop
 771
 772     def get_spr_msb(self):
 773         dec_insn = yield self.dec2.e.do.insn
 774         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 775
 776     def call(self, name):
 777         """call(opcode) - the primary execution point for instructions
 778         """
 779         name = name.strip()  # remove spaces if not already done so
 780         if self.halted:
 781             print("halted - not executing", name)
 782             return
 783
 784         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 785         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 786         asmop = yield from self.get_assembly_name()
 787         print("call", name, asmop)
 788
 789         # check privileged
 790         int_op = yield self.dec2.dec.op.internal_op
 791         spr_msb = yield from self.get_spr_msb()
 792
 793         instr_is_privileged = False
 794         if int_op in [MicrOp.OP_ATTN.value,
 795                       MicrOp.OP_MFMSR.value,
 796                       MicrOp.OP_MTMSR.value,
 797                       MicrOp.OP_MTMSRD.value,
 798                       # TODO: OP_TLBIE
 799                       MicrOp.OP_RFID.value]:
 800             instr_is_privileged = True
 801         if int_op in [MicrOp.OP_MFSPR.value,
 802                       MicrOp.OP_MTSPR.value] and spr_msb:
 803             instr_is_privileged = True
 804
 805         print("is priv", instr_is_privileged, hex(self.msr.value),
 806               self.msr[MSRb.PR])
 807         # check MSR priv bit and whether op is privileged: if so, throw trap
 808         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 809             self.TRAP(0x700, PIb.PRIV)
 810             self.namespace['NIA'] = self.trap_nia
 811             self.pc.update(self.namespace, self.is_svp64_mode)
 812             return
 813
 814         # check halted condition
 815         if name == 'attn':
 816             self.halted = True
 817             return
 818
 819         # check illegal instruction
 820         illegal = False
 821         if name not in ['mtcrf', 'mtocrf']:
 822             illegal = name != asmop
 823
 824         # sigh deal with setvl not being supported by binutils (.long)
 825         if asmop.startswith('setvl'):
 826             illegal = False
 827             name = 'setvl'
 828
 829         if illegal:
 830             print("illegal", name, asmop)
 831             self.TRAP(0x700, PIb.ILLEG)
 832             self.namespace['NIA'] = self.trap_nia
 833             self.pc.update(self.namespace, self.is_svp64_mode)
 834             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 835                   (name, asmop, self.pc.CIA.value))
 836             return
 837
 838         info = self.instrs[name]
 839         yield from self.prep_namespace(info.form, info.op_fields)
 840
 841         # preserve order of register names
 842         input_names = create_args(list(info.read_regs) +
 843                                   list(info.uninit_regs))
 844         print(input_names)
 845
 846         # get SVP64 entry for the current instruction
 847         sv_rm = self.svp64rm.instrs.get(name)
 848         if sv_rm is not None:
 849             dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
 850         else:
 851             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
 852         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 853
 854         # get SVSTATE VL (oh and print out some debug stuff)
 855         if self.is_svp64_mode:
 856             vl = self.svstate.vl.asint(msb0=True)
 857             srcstep = self.svstate.srcstep.asint(msb0=True)
 858             sv_a_nz = yield self.dec2.sv_a_nz
 859             in1 = yield self.dec2.e.read_reg1.data
 860             print ("SVP64: VL, srcstep, sv_a_nz, in1",
 861                     vl, srcstep, sv_a_nz, in1)
 862
 863         # VL=0 in SVP64 mode means "do nothing: skip instruction"
 864         if self.is_svp64_mode and vl == 0:
 865             self.pc.update(self.namespace, self.is_svp64_mode)
 866             print("SVP64: VL=0, end of call", self.namespace['CIA'],
 867                                        self.namespace['NIA'])
 868             return
 869
 870         # main input registers (RT, RA ...)
 871         inputs = []
 872         for name in input_names:
 873             # using PowerDecoder2, first, find the decoder index.
 874             # (mapping name RA RB RC RS to in1, in2, in3)
 875             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
 876             if regnum is None:
 877                 # doing this is not part of svp64, it's because output
 878                 # registers, to be modified, need to be in the namespace.
 879                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
 880
 881             # in case getting the register number is needed, _RA, _RB
 882             regname = "_" + name
 883             self.namespace[regname] = regnum
 884             print('reading reg %s %s' % (name, str(regnum)), is_vec)
 885             reg_val = self.gpr(regnum)
 886             inputs.append(reg_val)
 887
 888         # "special" registers
 889         for special in info.special_regs:
 890             if special in special_sprs:
 891                 inputs.append(self.spr[special])
 892             else:
 893                 inputs.append(self.namespace[special])
 894
 895         # clear trap (trap) NIA
 896         self.trap_nia = None
 897
 898         print("inputs", inputs)
 899         results = info.func(self, *inputs)
 900         print("results", results)
 901
 902         # "inject" decorator takes namespace from function locals: we need to
 903         # overwrite NIA being overwritten (sigh)
 904         if self.trap_nia is not None:
 905             self.namespace['NIA'] = self.trap_nia
 906
 907         print("after func", self.namespace['CIA'], self.namespace['NIA'])
 908
 909         # detect if CA/CA32 already in outputs (sra*, basically)
 910         already_done = 0
 911         if info.write_regs:
 912             output_names = create_args(info.write_regs)
 913             for name in output_names:
 914                 if name == 'CA':
 915                     already_done |= 1
 916                 if name == 'CA32':
 917                     already_done |= 2
 918
 919         print("carry already done?", bin(already_done))
 920         if hasattr(self.dec2.e.do, "output_carry"):
 921             carry_en = yield self.dec2.e.do.output_carry
 922         else:
 923             carry_en = False
 924         if carry_en:
 925             yield from self.handle_carry_(inputs, results, already_done)
 926
 927         # detect if overflow was in return result
 928         overflow = None
 929         if info.write_regs:
 930             for name, output in zip(output_names, results):
 931                 if name == 'overflow':
 932                     overflow = output
 933
 934         if hasattr(self.dec2.e.do, "oe"):
 935             ov_en = yield self.dec2.e.do.oe.oe
 936             ov_ok = yield self.dec2.e.do.oe.ok
 937         else:
 938             ov_en = False
 939             ov_ok = False
 940         print("internal overflow", overflow, ov_en, ov_ok)
 941         if ov_en & ov_ok:
 942             yield from self.handle_overflow(inputs, results, overflow)
 943
 944         if hasattr(self.dec2.e.do, "rc"):
 945             rc_en = yield self.dec2.e.do.rc.rc
 946         else:
 947             rc_en = False
 948         if rc_en:
 949             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
 950             self.handle_comparison(results, regnum)
 951
 952         # any modified return results?
 953         if info.write_regs:
 954             for name, output in zip(output_names, results):
 955                 if name == 'overflow':  # ignore, done already (above)
 956                     continue
 957                 if isinstance(output, int):
 958                     output = SelectableInt(output, 256)
 959                 if name in ['CA', 'CA32']:
 960                     if carry_en:
 961                         print("writing %s to XER" % name, output)
 962                         self.spr['XER'][XER_bits[name]] = output.value
 963                     else:
 964                         print("NOT writing %s to XER" % name, output)
 965                 elif name in info.special_regs:
 966                     print('writing special %s' % name, output, special_sprs)
 967                     if name in special_sprs:
 968                         self.spr[name] = output
 969                     else:
 970                         self.namespace[name].eq(output)
 971                     if name == 'MSR':
 972                         print('msr written', hex(self.msr.value))
 973                 else:
 974                     regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
 975                                                 name)
 976                     if regnum is None:
 977                         # temporary hack for not having 2nd output
 978                         regnum = yield getattr(self.decoder, name)
 979                         is_vec = False
 980                     print('writing reg %d %s' % (regnum, str(output)), is_vec)
 981                     if output.bits > 64:
 982                         output = SelectableInt(output.value, 64)
 983                     self.gpr[regnum] = output
 984
 985         # check if it is the SVSTATE.src/dest step that needs incrementing
 986         # this is our Sub-Program-Counter loop from 0 to VL-1
 987         if self.is_svp64_mode:
 988             # XXX twin predication TODO
 989             vl = self.svstate.vl.asint(msb0=True)
 990             mvl = self.svstate.maxvl.asint(msb0=True)
 991             srcstep = self.svstate.srcstep.asint(msb0=True)
 992             sv_ptype = yield self.dec2.dec.op.SV_Ptype
 993             no_out_vec = not (yield self.dec2.no_out_vec)
 994             no_in_vec = not (yield self.dec2.no_in_vec)
 995             print ("    svstate.vl", vl)
 996             print ("    svstate.mvl", mvl)
 997             print ("    svstate.srcstep", srcstep)
 998             print ("    no_out_vec", no_out_vec)
 999             print ("    no_in_vec", no_in_vec)
1000             print ("    sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
1001             # check if srcstep needs incrementing by one, stop PC advancing
1002             # svp64 loop can end early if the dest is scalar for single-pred
1003             # but for 2-pred both src/dest have to be checked.
1004             # XXX this might not be true! it may just be LD/ST
1005             if sv_ptype == SVPtype.P2.value:
1006                 svp64_is_vector = (no_out_vec or no_in_vec)
1007             else:
1008                 svp64_is_vector = no_out_vec
1009             if svp64_is_vector and srcstep != vl-1:
1010                 self.svstate.srcstep += SelectableInt(1, 7)
1011                 self.pc.NIA.value = self.pc.CIA.value
1012                 self.namespace['NIA'] = self.pc.NIA
1013                 self.namespace['SVSTATE'] = self.svstate.spr
1014                 print("end of sub-pc call", self.namespace['CIA'],
1015                                      self.namespace['NIA'])
1016                 return # DO NOT allow PC to update whilst Sub-PC loop running
1017             # reset to zero
1018             self.svstate.srcstep[0:7] = 0
1019             print ("    svstate.srcstep loop end (PC to update)")
1020             self.pc.update_nia(self.is_svp64_mode)
1021             self.namespace['NIA'] = self.pc.NIA
1022             self.namespace['SVSTATE'] = self.svstate.spr
1023
1024         # UPDATE program counter
1025         self.pc.update(self.namespace, self.is_svp64_mode)
1026         self.svstate.spr = self.namespace['SVSTATE']
1027         print("end of call", self.namespace['CIA'],
1028                              self.namespace['NIA'],
1029                              self.namespace['SVSTATE'])
1030
1031
1032 def inject():
1033     """Decorator factory.
1034
1035     this decorator will "inject" variables into the function's namespace,
1036     from the *dictionary* in self.namespace.  it therefore becomes possible
1037     to make it look like a whole stack of variables which would otherwise
1038     need "self." inserted in front of them (*and* for those variables to be
1039     added to the instance) "appear" in the function.
1040
1041     "self.namespace['SI']" for example becomes accessible as just "SI" but
1042     *only* inside the function, when decorated.
1043     """
1044     def variable_injector(func):
1045         @wraps(func)
1046         def decorator(*args, **kwargs):
1047             try:
1048                 func_globals = func.__globals__  # Python 2.6+
1049             except AttributeError:
1050                 func_globals = func.func_globals  # Earlier versions.
1051
1052             context = args[0].namespace  # variables to be injected
1053             saved_values = func_globals.copy()  # Shallow copy of dict.
1054             func_globals.update(context)
1055             result = func(*args, **kwargs)
1056             print("globals after", func_globals['CIA'], func_globals['NIA'])
1057             print("args[0]", args[0].namespace['CIA'],
1058                   args[0].namespace['NIA'],
1059                   args[0].namespace['SVSTATE'])
1060             args[0].namespace = func_globals
1061             #exec (func.__code__, func_globals)
1062
1063             # finally:
1064             #    func_globals = saved_values  # Undo changes.
1065
1066             return result
1067
1068         return decorator
1069
1070     return variable_injector
1071
1072