1 """core of the python-based POWER9 simulator
3 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
4 not speed, it is for both learning and educational purposes, as well as
5 a method of verifying the HDL.
8 from functools
import wraps
9 from soc
.decoder
.orderedset
import OrderedSet
10 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
12 from soc
.decoder
.power_enums
import spr_dict
, XER_bits
, insns
, InternalOp
13 from soc
.decoder
.helpers
import exts
14 from collections
import namedtuple
18 instruction_info
= namedtuple('instruction_info',
19 'func read_regs uninit_regs write_regs ' + \
20 'special_regs op_fields form asmregs')
30 def swap_order(x
, nbytes
):
31 x
= x
.to_bytes(nbytes
, byteorder
='little')
32 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
36 def create_args(reglist
, extra
=None):
48 def __init__(self
, row_bytes
=8, initial_mem
=None):
50 self
.bytes_per_word
= row_bytes
51 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
52 print ("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
56 # different types of memory data structures recognised (for convenience)
57 if isinstance(initial_mem
, list):
58 initial_mem
= (0, initial_mem
)
59 if isinstance(initial_mem
, tuple):
60 startaddr
, mem
= initial_mem
62 for i
, val
in enumerate(mem
):
63 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
65 for addr
, (val
, width
) in initial_mem
.items():
66 #val = swap_order(val, width)
67 self
.st(addr
, val
, width
, swap
=False)
69 def _get_shifter_mask(self
, wid
, remainder
):
70 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
72 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
74 shifter
= remainder
* 8
75 mask
= (1 << (wid
* 8)) - 1
76 print ("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
79 # TODO: Implement ld/st of lesser width
80 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
81 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
82 remainder
= address
& (self
.bytes_per_word
- 1)
83 address
= address
>> self
.word_log2
84 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
85 if address
in self
.mem
:
86 val
= self
.mem
[address
]
91 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
93 if width
!= self
.bytes_per_word
:
94 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
95 print ("masking", hex(val
), hex(mask
<<shifter
), shifter
)
96 val
= val
& (mask
<< shifter
)
99 val
= swap_order(val
, width
)
100 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
103 def st(self
, addr
, v
, width
=8, swap
=True):
105 remainder
= addr
& (self
.bytes_per_word
- 1)
106 addr
= addr
>> self
.word_log2
107 print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v
,
108 staddr
, addr
, remainder
, swap
))
109 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
111 v
= swap_order(v
, width
)
112 if width
!= self
.bytes_per_word
:
117 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
118 val
&= ~
(mask
<< shifter
)
123 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
125 def __call__(self
, addr
, sz
):
126 val
= self
.ld(addr
.value
, sz
)
127 print ("memread", addr
, sz
, val
)
128 return SelectableInt(val
, sz
*8)
130 def memassign(self
, addr
, sz
, val
):
131 print ("memassign", addr
, sz
, val
)
132 self
.st(addr
.value
, val
.value
, sz
)
136 def __init__(self
, decoder
, regfile
):
140 self
[i
] = SelectableInt(regfile
[i
], 64)
142 def __call__(self
, ridx
):
145 def set_form(self
, form
):
148 def getz(self
, rnum
):
149 #rnum = rnum.value # only SelectableInt allowed
150 print("GPR getzero", rnum
)
152 return SelectableInt(0, 64)
155 def _get_regnum(self
, attr
):
156 getform
= self
.sd
.sigforms
[self
.form
]
157 rnum
= getattr(getform
, attr
)
160 def ___getitem__(self
, attr
):
161 print("GPR getitem", attr
)
162 rnum
= self
._get
_regnum
(attr
)
163 return self
.regfile
[rnum
]
166 for i
in range(0, len(self
), 8):
169 s
.append("%08x" % self
[i
+j
].value
)
171 print("reg", "%2d" % i
, s
)
174 def __init__(self
, pc_init
=0):
175 self
.CIA
= SelectableInt(pc_init
, 64)
176 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
178 def update(self
, namespace
):
179 self
.CIA
= namespace
['NIA'].narrow(64)
180 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
181 namespace
['CIA'] = self
.CIA
182 namespace
['NIA'] = self
.NIA
186 def __init__(self
, dec2
, initial_sprs
={}):
189 self
.update(initial_sprs
)
191 def __getitem__(self
, key
):
192 # if key in special_sprs get the special spr, otherwise return key
193 if isinstance(key
, SelectableInt
):
195 key
= special_sprs
.get(key
, key
)
197 return dict.__getitem
__(self
, key
)
200 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
201 return dict.__getitem
__(self
, key
)
203 def __setitem__(self
, key
, value
):
204 if isinstance(key
, SelectableInt
):
206 key
= special_sprs
.get(key
, key
)
207 dict.__setitem
__(self
, key
, value
)
209 def __call__(self
, ridx
):
214 # decoder2 - an instance of power_decoder2
215 # regfile - a list of initial values for the registers
216 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
217 # respect_pc - tracks the program counter. requires initial_insns
218 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
219 initial_mem
=None, initial_msr
=0,
220 initial_insns
=None, respect_pc
=False,
223 self
.respect_pc
= respect_pc
224 if initial_sprs
is None:
226 if initial_mem
is None:
228 if initial_insns
is None:
230 assert self
.respect_pc
== False, "instructions required to honor pc"
232 print ("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
234 # "fake program counter" mode (for unit testing)
237 if isinstance(initial_mem
, tuple):
238 self
.fake_pc
= initial_mem
[0]
240 # disassembly: we need this for now (not given from the decoder)
241 self
.disassembly
= {}
243 for i
, code
in enumerate(disassembly
):
244 self
.disassembly
[i
*4 + self
.fake_pc
] = code
246 # set up registers, instruction memory, data memory, PC, SPRs, MSR
247 self
.gpr
= GPR(decoder2
, regfile
)
248 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
249 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
251 self
.spr
= SPR(decoder2
, initial_sprs
)
252 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
255 # FPR (same as GPR except for FP nums)
256 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
257 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
258 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
259 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
261 # 2.3.2 LR (actually SPR #8) -- Done
262 # 2.3.3 CTR (actually SPR #9) -- Done
263 # 2.3.4 TAR (actually SPR #815)
264 # 3.2.2 p45 XER (actually SPR #1) -- Done
265 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
267 # create CR then allow portions of it to be "selectable" (below)
268 self
._cr
= SelectableInt(initial_cr
, 64) # underlying reg
269 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
271 # "undefined", just set to variable-bit-width int (use exts "max")
272 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
274 self
.namespace
= {'GPR': self
.gpr
,
277 'memassign': self
.memassign
,
282 'undefined': self
.undefined
,
283 'mode_is_64bit': True,
287 # field-selectable versions of Condition Register TODO check bitranges?
290 bits
= tuple(range(i
*4, (i
+1)*4))# errr... maybe?
291 _cr
= FieldSelectableInt(self
.cr
, bits
)
293 self
.namespace
["CR%d" % i
] = _cr
295 self
.decoder
= decoder2
.dec
298 def TRAP(self
, trap_addr
=0x700):
300 # store CIA(+4?) in SRR0, set NIA to 0x700
301 # store MSR in SRR1, set MSR to um errr something, have to check spec
303 def memassign(self
, ea
, sz
, val
):
304 self
.mem
.memassign(ea
, sz
, val
)
306 def prep_namespace(self
, formname
, op_fields
):
307 # TODO: get field names from form in decoder*1* (not decoder2)
308 # decoder2 is hand-created, and decoder1.sigform is auto-generated
310 # then "yield" fields only from op_fields rather than hard-coded
312 fields
= self
.decoder
.sigforms
[formname
]
313 for name
in op_fields
:
315 sig
= getattr(fields
, name
.upper())
317 sig
= getattr(fields
, name
)
319 if name
in ['BF', 'BFA']:
320 self
.namespace
[name
] = val
322 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
324 self
.namespace
['XER'] = self
.spr
['XER']
325 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
326 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
328 def handle_carry_(self
, inputs
, outputs
, already_done
):
329 inv_a
= yield self
.dec2
.e
.invert_a
331 inputs
[0] = ~inputs
[0]
333 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
335 imm
= yield self
.dec2
.e
.imm_data
.data
336 inputs
.append(SelectableInt(imm
, 64))
337 assert len(outputs
) >= 1
339 gts
= [(x
> output
) for x
in inputs
]
341 cy
= 1 if any(gts
) else 0
342 if not (1 & already_done
):
343 self
.spr
['XER'][XER_bits
['CA']] = cy
345 print ("inputs", inputs
)
347 gts
= [(x
[32:64] > output
[32:64]) == SelectableInt(1, 1)
349 cy32
= 1 if any(gts
) else 0
350 if not (2 & already_done
):
351 self
.spr
['XER'][XER_bits
['CA32']] = cy32
353 def handle_overflow(self
, inputs
, outputs
):
354 inv_a
= yield self
.dec2
.e
.invert_a
356 inputs
[0] = ~inputs
[0]
358 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
360 imm
= yield self
.dec2
.e
.imm_data
.data
361 inputs
.append(SelectableInt(imm
, 64))
362 assert len(outputs
) >= 1
363 print ("handle_overflow", inputs
, outputs
)
368 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
369 output_sgn
= exts(output
.value
, output
.bits
) < 0
370 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
371 output_sgn
!= input_sgn
[0] else 0
374 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
375 output32_sgn
= exts(output
.value
, 32) < 0
376 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
377 output32_sgn
!= input32_sgn
[0] else 0
379 self
.spr
['XER'][XER_bits
['OV']] = ov
380 self
.spr
['XER'][XER_bits
['OV32']] = ov32
381 so
= self
.spr
['XER'][XER_bits
['SO']]
383 self
.spr
['XER'][XER_bits
['SO']] = so
385 def handle_comparison(self
, outputs
):
387 out
= exts(out
.value
, out
.bits
)
388 zero
= SelectableInt(out
== 0, 1)
389 positive
= SelectableInt(out
> 0, 1)
390 negative
= SelectableInt(out
< 0, 1)
391 SO
= self
.spr
['XER'][XER_bits
['SO']]
392 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
393 self
.crl
[0].eq(cr_field
)
395 def set_pc(self
, pc_val
):
396 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
397 self
.pc
.update(self
.namespace
)
400 """set up one instruction
403 pc
= self
.pc
.CIA
.value
407 ins
= self
.imem
.ld(pc
, 4, False, True)
409 raise KeyError("no instruction at 0x%x" % pc
)
410 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
411 print ("NIA, CIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
413 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
414 yield self
.dec2
.dec
.bigendian
.eq(0) # little / big?
416 def execute_one(self
):
417 """execute one instruction
419 # get the disassembly code for this instruction
420 code
= self
.disassembly
[self
._pc
]
421 print("sim-execute", hex(self
._pc
), code
)
422 opname
= code
.split(' ')[0]
423 yield from self
.call(opname
)
425 if not self
.respect_pc
:
427 print ("NIA, CIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
429 def get_assembly_name(self
):
430 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
431 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
432 asmcode
= yield self
.dec2
.dec
.op
.asmcode
433 asmop
= insns
.get(asmcode
, None)
435 # sigh reconstruct the assembly instruction name
436 ov_en
= yield self
.dec2
.e
.oe
.oe
437 ov_ok
= yield self
.dec2
.e
.oe
.ok
440 lk
= yield self
.dec2
.e
.lk
443 int_op
= yield self
.dec2
.dec
.op
.internal_op
444 print ("int_op", int_op
)
445 if int_op
in [InternalOp
.OP_B
.value
, InternalOp
.OP_BC
.value
]:
446 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
450 if int_op
== InternalOp
.OP_MFCR
.value
:
451 dec_insn
= yield self
.dec2
.e
.insn
452 if dec_insn
& (1<<20) != 0: # sigh
456 # XXX TODO: for whatever weird reason this doesn't work
457 # https://bugs.libre-soc.org/show_bug.cgi?id=390
458 if int_op
== InternalOp
.OP_MTCRF
.value
:
459 dec_insn
= yield self
.dec2
.e
.insn
460 if dec_insn
& (1<<20) != 0: # sigh
466 def call(self
, name
):
467 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
468 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
469 asmop
= yield from self
.get_assembly_name()
470 print ("call", name
, asmop
)
471 if name
not in ['mtcrf', 'mtocrf']:
472 assert name
== asmop
, "name %s != %s" % (name
, asmop
)
474 info
= self
.instrs
[name
]
475 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
477 # preserve order of register names
478 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
481 # main registers (RT, RA ...)
483 for name
in input_names
:
484 regnum
= yield getattr(self
.decoder
, name
)
486 self
.namespace
[regname
] = regnum
487 print('reading reg %d' % regnum
)
488 inputs
.append(self
.gpr(regnum
))
490 # "special" registers
491 for special
in info
.special_regs
:
492 if special
in special_sprs
:
493 inputs
.append(self
.spr
[special
])
495 inputs
.append(self
.namespace
[special
])
498 results
= info
.func(self
, *inputs
)
501 # detect if CA/CA32 already in outputs (sra*, basically)
504 output_names
= create_args(info
.write_regs
)
505 for name
in output_names
:
511 print ("carry already done?", bin(already_done
))
512 carry_en
= yield self
.dec2
.e
.output_carry
514 yield from self
.handle_carry_(inputs
, results
, already_done
)
515 ov_en
= yield self
.dec2
.e
.oe
.oe
516 ov_ok
= yield self
.dec2
.e
.oe
.ok
518 yield from self
.handle_overflow(inputs
, results
)
519 rc_en
= yield self
.dec2
.e
.rc
.data
521 self
.handle_comparison(results
)
523 # any modified return results?
525 for name
, output
in zip(output_names
, results
):
526 if isinstance(output
, int):
527 output
= SelectableInt(output
, 256)
528 if name
in ['CA', 'CA32']:
530 print ("writing %s to XER" % name
, output
)
531 self
.spr
['XER'][XER_bits
[name
]] = output
.value
533 print ("NOT writing %s to XER" % name
, output
)
534 elif name
in info
.special_regs
:
535 print('writing special %s' % name
, output
, special_sprs
)
536 if name
in special_sprs
:
537 self
.spr
[name
] = output
539 self
.namespace
[name
].eq(output
)
541 regnum
= yield getattr(self
.decoder
, name
)
542 print('writing reg %d %s' % (regnum
, str(output
)))
544 output
= SelectableInt(output
.value
, 64)
545 self
.gpr
[regnum
] = output
547 # update program counter
548 self
.pc
.update(self
.namespace
)
552 """Decorator factory.
554 this decorator will "inject" variables into the function's namespace,
555 from the *dictionary* in self.namespace. it therefore becomes possible
556 to make it look like a whole stack of variables which would otherwise
557 need "self." inserted in front of them (*and* for those variables to be
558 added to the instance) "appear" in the function.
560 "self.namespace['SI']" for example becomes accessible as just "SI" but
561 *only* inside the function, when decorated.
563 def variable_injector(func
):
565 def decorator(*args
, **kwargs
):
567 func_globals
= func
.__globals
__ # Python 2.6+
568 except AttributeError:
569 func_globals
= func
.func_globals
# Earlier versions.
571 context
= args
[0].namespace
# variables to be injected
572 saved_values
= func_globals
.copy() # Shallow copy of dict.
573 func_globals
.update(context
)
574 result
= func(*args
, **kwargs
)
575 args
[0].namespace
= func_globals
576 #exec (func.__code__, func_globals)
579 # func_globals = saved_values # Undo changes.
585 return variable_injector