src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from soc.decoder.power_enums import spr_dict, XER_bits
   6 from soc.decoder.helpers import exts
   7 from collections import namedtuple
   8 import math
   9
  10 instruction_info = namedtuple('instruction_info',
  11                               'func read_regs uninit_regs write_regs ' + \
  12                               'special_regs op_fields form asmregs')
  13
  14 special_sprs = {
  15     'LR': 8,
  16     'CTR': 9,
  17     'TAR': 815,
  18     'XER': 1,
  19     'VRSAVE': 256}
  20
  21
  22 def create_args(reglist, extra=None):
  23     args = OrderedSet()
  24     for reg in reglist:
  25         args.add(reg)
  26     args = list(args)
  27     if extra:
  28         args = [extra] + args
  29     return args
  30
  31
  32 class Mem:
  33
  34     def __init__(self, bytes_per_word=8, initial_mem=None):
  35         self.mem = {}
  36         self.bytes_per_word = bytes_per_word
  37         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  38         if initial_mem:
  39             for addr, (val, width) in initial_mem.items():
  40                 self.st(addr, val, width)
  41
  42     def _get_shifter_mask(self, width, remainder):
  43         shifter = ((self.bytes_per_word - width) - remainder) * \
  44             8  # bits per byte
  45         mask = (1 << (width * 8)) - 1
  46         return shifter, mask
  47
  48     # TODO: Implement ld/st of lesser width
  49     def ld(self, address, width=8):
  50         remainder = address & (self.bytes_per_word - 1)
  51         address = address >> self.word_log2
  52         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  53         if address in self.mem:
  54             val = self.mem[address]
  55         else:
  56             val = 0
  57
  58         if width != self.bytes_per_word:
  59             shifter, mask = self._get_shifter_mask(width, remainder)
  60             val = val & (mask << shifter)
  61             val >>= shifter
  62         print("Read {:x} from addr {:x}".format(val, address))
  63         return val
  64
  65     def st(self, address, value, width=8):
  66         remainder = address & (self.bytes_per_word - 1)
  67         address = address >> self.word_log2
  68         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  69         print("Writing {:x} to addr {:x}".format(value, address))
  70         if width != self.bytes_per_word:
  71             if address in self.mem:
  72                 val = self.mem[address]
  73             else:
  74                 val = 0
  75             shifter, mask = self._get_shifter_mask(width, remainder)
  76             val &= ~(mask << shifter)
  77             val |= value << shifter
  78             self.mem[address] = val
  79         else:
  80             self.mem[address] = value
  81
  82     def __call__(self, addr, sz):
  83         val = self.ld(addr.value, sz)
  84         print ("memread", addr, sz, val)
  85         return SelectableInt(val, sz*8)
  86
  87     def memassign(self, addr, sz, val):
  88         print ("memassign", addr, sz, val)
  89         self.st(addr.value, val.value, sz)
  90
  91
  92 class GPR(dict):
  93     def __init__(self, decoder, regfile):
  94         dict.__init__(self)
  95         self.sd = decoder
  96         for i in range(32):
  97             self[i] = SelectableInt(regfile[i], 64)
  98
  99     def __call__(self, ridx):
 100         return self[ridx]
 101
 102     def set_form(self, form):
 103         self.form = form
 104
 105     def getz(self, rnum):
 106         #rnum = rnum.value # only SelectableInt allowed
 107         print("GPR getzero", rnum)
 108         if rnum == 0:
 109             return SelectableInt(0, 64)
 110         return self[rnum]
 111
 112     def _get_regnum(self, attr):
 113         getform = self.sd.sigforms[self.form]
 114         rnum = getattr(getform, attr)
 115         return rnum
 116
 117     def ___getitem__(self, attr):
 118         print("GPR getitem", attr)
 119         rnum = self._get_regnum(attr)
 120         return self.regfile[rnum]
 121
 122     def dump(self):
 123         for i in range(0, len(self), 8):
 124             s = []
 125             for j in range(8):
 126                 s.append("%08x" % self[i+j].value)
 127             s = ' '.join(s)
 128             print("reg", "%2d" % i, s)
 129
 130 class PC:
 131     def __init__(self, pc_init=0):
 132         self.CIA = SelectableInt(pc_init, 64)
 133         self.NIA = self.CIA + SelectableInt(4, 64)
 134
 135     def update(self, namespace):
 136         self.CIA = namespace['NIA'].narrow(64)
 137         self.NIA = self.CIA + SelectableInt(4, 64)
 138         namespace['CIA'] = self.CIA
 139         namespace['NIA'] = self.NIA
 140
 141
 142 class SPR(dict):
 143     def __init__(self, dec2, initial_sprs={}):
 144         self.sd = dec2
 145         dict.__init__(self)
 146         self.update(initial_sprs)
 147
 148     def __getitem__(self, key):
 149         # if key in special_sprs get the special spr, otherwise return key
 150         if isinstance(key, SelectableInt):
 151             key = key.value
 152         key = special_sprs.get(key, key)
 153         if key in self:
 154             return dict.__getitem__(self, key)
 155         else:
 156             info = spr_dict[key]
 157             dict.__setitem__(self, key, SelectableInt(0, info.length))
 158             return dict.__getitem__(self, key)
 159
 160     def __setitem__(self, key, value):
 161         if isinstance(key, SelectableInt):
 162             key = key.value
 163         key = special_sprs.get(key, key)
 164         dict.__setitem__(self, key, value)
 165
 166     def __call__(self, ridx):
 167         return self[ridx]
 168
 169
 170
 171 class ISACaller:
 172     # decoder2 - an instance of power_decoder2
 173     # regfile - a list of initial values for the registers
 174     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 175                        initial_mem=None):
 176         if initial_sprs is None:
 177             initial_sprs = {}
 178         if initial_mem is None:
 179             initial_mem = {}
 180         self.gpr = GPR(decoder2, regfile)
 181         self.mem = Mem(initial_mem=initial_mem)
 182         self.pc = PC()
 183         self.spr = SPR(decoder2, initial_sprs)
 184         # TODO, needed here:
 185         # FPR (same as GPR except for FP nums)
 186         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 187         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 188         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 189         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 190         #         -- Done
 191         # 2.3.2 LR   (actually SPR #8) -- Done
 192         # 2.3.3 CTR  (actually SPR #9) -- Done
 193         # 2.3.4 TAR  (actually SPR #815)
 194         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 195         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 196
 197         # create CR then allow portions of it to be "selectable" (below)
 198         self._cr = SelectableInt(initial_cr, 64) # underlying reg
 199         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 200
 201         # "undefined", just set to variable-bit-width int (use exts "max")
 202         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 203
 204         self.namespace = {'GPR': self.gpr,
 205                           'MEM': self.mem,
 206                           'SPR': self.spr,
 207                           'memassign': self.memassign,
 208                           'NIA': self.pc.NIA,
 209                           'CIA': self.pc.CIA,
 210                           'CR': self.cr,
 211                           'undefined': self.undefined,
 212                           'mode_is_64bit': True,
 213                           'SO': XER_bits['SO']
 214                           }
 215
 216         # field-selectable versions of Condition Register TODO check bitranges?
 217         self.crl = []
 218         for i in range(8):
 219             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 220             _cr = FieldSelectableInt(self.cr, bits)
 221             self.crl.append(_cr)
 222             self.namespace["CR%d" % i] = _cr
 223
 224         self.decoder = decoder2.dec
 225         self.dec2 = decoder2
 226
 227     def memassign(self, ea, sz, val):
 228         self.mem.memassign(ea, sz, val)
 229
 230     def prep_namespace(self, formname, op_fields):
 231         # TODO: get field names from form in decoder*1* (not decoder2)
 232         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 233         # from spec
 234         # then "yield" fields only from op_fields rather than hard-coded
 235         # list, here.
 236         fields = self.decoder.sigforms[formname]
 237         for name in op_fields:
 238             if name == 'spr':
 239                 sig = getattr(fields, name.upper())
 240             else:
 241                 sig = getattr(fields, name)
 242             val = yield sig
 243             if name in ['BF', 'BFA']:
 244                 self.namespace[name] = val
 245             else:
 246                 self.namespace[name] = SelectableInt(val, sig.width)
 247
 248         self.namespace['XER'] = self.spr['XER']
 249         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 250
 251     def handle_carry_(self, inputs, outputs):
 252         inv_a = yield self.dec2.e.invert_a
 253         if inv_a:
 254             inputs[0] = ~inputs[0]
 255
 256         imm_ok = yield self.dec2.e.imm_data.ok
 257         if imm_ok:
 258             imm = yield self.dec2.e.imm_data.data
 259             inputs.append(SelectableInt(imm, 64))
 260         assert len(outputs) >= 1
 261         output = outputs[0]
 262         gts = [(x > output) for x in inputs]
 263         print(gts)
 264         cy = 1 if any(gts) else 0
 265         self.spr['XER'][XER_bits['CA']] = cy
 266
 267
 268         # 32 bit carry
 269         gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
 270                for x in inputs]
 271         cy32 = 1 if any(gts) else 0
 272         self.spr['XER'][XER_bits['CA32']] = cy32
 273
 274     def handle_overflow(self, inputs, outputs):
 275         inv_a = yield self.dec2.e.invert_a
 276         if inv_a:
 277             inputs[0] = ~inputs[0]
 278
 279         imm_ok = yield self.dec2.e.imm_data.ok
 280         if imm_ok:
 281             imm = yield self.dec2.e.imm_data.data
 282             inputs.append(SelectableInt(imm, 64))
 283         assert len(outputs) >= 1
 284         if len(inputs) >= 2:
 285             output = outputs[0]
 286             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 287             output_sgn = exts(output.value, output.bits) < 0
 288             ov = 1 if input_sgn[0] == input_sgn[1] and \
 289                 output_sgn != input_sgn[0] else 0
 290
 291             self.spr['XER'][XER_bits['OV']] = ov
 292             so = self.spr['XER'][XER_bits['SO']]
 293             so = so | ov
 294             self.spr['XER'][XER_bits['SO']] = so
 295
 296
 297
 298     def handle_comparison(self, outputs):
 299         out = outputs[0]
 300         out = exts(out.value, out.bits)
 301         zero = SelectableInt(out == 0, 1)
 302         positive = SelectableInt(out > 0, 1)
 303         negative = SelectableInt(out < 0, 1)
 304         SO = self.spr['XER'][XER_bits['SO']]
 305         cr_field = selectconcat(negative, positive, zero, SO)
 306         self.crl[0].eq(cr_field)
 307
 308     def set_pc(self, pc_val):
 309         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 310         self.pc.update(self.namespace)
 311
 312
 313     def call(self, name):
 314         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 315         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 316         info = self.instrs[name]
 317         yield from self.prep_namespace(info.form, info.op_fields)
 318
 319         # preserve order of register names
 320         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 321         print(input_names)
 322
 323         # main registers (RT, RA ...)
 324         inputs = []
 325         for name in input_names:
 326             regnum = yield getattr(self.decoder, name)
 327             regname = "_" + name
 328             self.namespace[regname] = regnum
 329             print('reading reg %d' % regnum)
 330             inputs.append(self.gpr(regnum))
 331
 332         # "special" registers
 333         for special in info.special_regs:
 334             if special in special_sprs:
 335                 inputs.append(self.spr[special])
 336             else:
 337                 inputs.append(self.namespace[special])
 338
 339         print(inputs)
 340         results = info.func(self, *inputs)
 341         print(results)
 342
 343         carry_en = yield self.dec2.e.output_carry
 344         if carry_en:
 345             yield from self.handle_carry_(inputs, results)
 346         ov_en = yield self.dec2.e.oe
 347         if ov_en:
 348             yield from self.handle_overflow(inputs, results)
 349         rc_en = yield self.dec2.e.rc.data
 350         if rc_en:
 351             self.handle_comparison(results)
 352
 353         # any modified return results?
 354         if info.write_regs:
 355             output_names = create_args(info.write_regs)
 356             for name, output in zip(output_names, results):
 357                 if isinstance(output, int):
 358                     output = SelectableInt(output, 256)
 359                 if name in info.special_regs:
 360                     print('writing special %s' % name, output)
 361                     if name in special_sprs:
 362                         self.spr[name] = output
 363                     else:
 364                         self.namespace[name].eq(output)
 365                 else:
 366                     regnum = yield getattr(self.decoder, name)
 367                     print('writing reg %d %s' % (regnum, str(output)))
 368                     if output.bits > 64:
 369                         output = SelectableInt(output.value, 64)
 370                     self.gpr[regnum] = output
 371
 372         # update program counter
 373         self.pc.update(self.namespace)
 374
 375
 376 def inject():
 377     """ Decorator factory. """
 378     def variable_injector(func):
 379         @wraps(func)
 380         def decorator(*args, **kwargs):
 381             try:
 382                 func_globals = func.__globals__  # Python 2.6+
 383             except AttributeError:
 384                 func_globals = func.func_globals  # Earlier versions.
 385
 386             context = args[0].namespace
 387             saved_values = func_globals.copy()  # Shallow copy of dict.
 388             func_globals.update(context)
 389             result = func(*args, **kwargs)
 390             args[0].namespace = func_globals
 391             #exec (func.__code__, func_globals)
 392
 393             #finally:
 394             #    func_globals = saved_values  # Undo changes.
 395
 396             return result
 397
 398         return decorator
 399
 400     return variable_injector
 401