Assemble the SV64 prefix from its subfields using SVP64PrefixFields
[soc.git] / src / soc / decoder / isa / caller.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
14 """
15
16 from nmigen.back.pysim import Settle
17 from functools import wraps
18 from copy import copy
19 from soc.decoder.orderedset import OrderedSet
20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
21 selectconcat)
22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
23 insns, MicrOp, In1Sel, In2Sel, In3Sel,
24 OutSel, CROutSel)
25 from soc.decoder.helpers import exts, gtu, ltu, undefined
26 from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
27 from soc.decoder.power_svp64 import SVP64RM, decode_extra
28
29 from collections import namedtuple
30 import math
31 import sys
32
33 instruction_info = namedtuple('instruction_info',
34 'func read_regs uninit_regs write_regs ' +
35 'special_regs op_fields form asmregs')
36
37 special_sprs = {
38 'LR': 8,
39 'CTR': 9,
40 'TAR': 815,
41 'XER': 1,
42 'VRSAVE': 256}
43
44
45 def swap_order(x, nbytes):
46 x = x.to_bytes(nbytes, byteorder='little')
47 x = int.from_bytes(x, byteorder='big', signed=False)
48 return x
49
50
51 REG_SORT_ORDER = {
52 # TODO (lkcl): adjust other registers that should be in a particular order
53 # probably CA, CA32, and CR
54 "RT": 0,
55 "RA": 0,
56 "RB": 0,
57 "RS": 0,
58 "CR": 0,
59 "LR": 0,
60 "CTR": 0,
61 "TAR": 0,
62 "CA": 0,
63 "CA32": 0,
64 "MSR": 0,
65
66 "overflow": 1,
67 }
68
69
70 def create_args(reglist, extra=None):
71 retval = list(OrderedSet(reglist))
72 retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
73 if extra is not None:
74 return [extra] + retval
75 return retval
76
77
78 class Mem:
79
80 def __init__(self, row_bytes=8, initial_mem=None):
81 self.mem = {}
82 self.bytes_per_word = row_bytes
83 self.word_log2 = math.ceil(math.log2(row_bytes))
84 print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
85 if not initial_mem:
86 return
87
88 # different types of memory data structures recognised (for convenience)
89 if isinstance(initial_mem, list):
90 initial_mem = (0, initial_mem)
91 if isinstance(initial_mem, tuple):
92 startaddr, mem = initial_mem
93 initial_mem = {}
94 for i, val in enumerate(mem):
95 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
96
97 for addr, (val, width) in initial_mem.items():
98 #val = swap_order(val, width)
99 self.st(addr, val, width, swap=False)
100
101 def _get_shifter_mask(self, wid, remainder):
102 shifter = ((self.bytes_per_word - wid) - remainder) * \
103 8 # bits per byte
104 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
105 # BE/LE mode?
106 shifter = remainder * 8
107 mask = (1 << (wid * 8)) - 1
108 print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
109 return shifter, mask
110
111 # TODO: Implement ld/st of lesser width
112 def ld(self, address, width=8, swap=True, check_in_mem=False):
113 print("ld from addr 0x{:x} width {:d}".format(address, width))
114 remainder = address & (self.bytes_per_word - 1)
115 address = address >> self.word_log2
116 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
117 if address in self.mem:
118 val = self.mem[address]
119 elif check_in_mem:
120 return None
121 else:
122 val = 0
123 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
124
125 if width != self.bytes_per_word:
126 shifter, mask = self._get_shifter_mask(width, remainder)
127 print("masking", hex(val), hex(mask << shifter), shifter)
128 val = val & (mask << shifter)
129 val >>= shifter
130 if swap:
131 val = swap_order(val, width)
132 print("Read 0x{:x} from addr 0x{:x}".format(val, address))
133 return val
134
135 def st(self, addr, v, width=8, swap=True):
136 staddr = addr
137 remainder = addr & (self.bytes_per_word - 1)
138 addr = addr >> self.word_log2
139 print("Writing 0x{:x} to ST 0x{:x} "
140 "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
141 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
142 if swap:
143 v = swap_order(v, width)
144 if width != self.bytes_per_word:
145 if addr in self.mem:
146 val = self.mem[addr]
147 else:
148 val = 0
149 shifter, mask = self._get_shifter_mask(width, remainder)
150 val &= ~(mask << shifter)
151 val |= v << shifter
152 self.mem[addr] = val
153 else:
154 self.mem[addr] = v
155 print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
156
157 def __call__(self, addr, sz):
158 val = self.ld(addr.value, sz, swap=False)
159 print("memread", addr, sz, val)
160 return SelectableInt(val, sz*8)
161
162 def memassign(self, addr, sz, val):
163 print("memassign", addr, sz, val)
164 self.st(addr.value, val.value, sz, swap=False)
165
166
167 class GPR(dict):
168 def __init__(self, decoder, isacaller, svstate, regfile):
169 dict.__init__(self)
170 self.sd = decoder
171 self.isacaller = isacaller
172 self.svstate = svstate
173 for i in range(32):
174 self[i] = SelectableInt(regfile[i], 64)
175
176 def __call__(self, ridx):
177 return self[ridx]
178
179 def set_form(self, form):
180 self.form = form
181
182 def getz(self, rnum):
183 # rnum = rnum.value # only SelectableInt allowed
184 print("GPR getzero", rnum)
185 if rnum == 0:
186 return SelectableInt(0, 64)
187 return self[rnum]
188
189 def _get_regnum(self, attr):
190 getform = self.sd.sigforms[self.form]
191 rnum = getattr(getform, attr)
192 return rnum
193
194 def ___getitem__(self, attr):
195 """ XXX currently not used
196 """
197 rnum = self._get_regnum(attr)
198 offs = self.svstate.srcstep
199 print("GPR getitem", attr, rnum, "srcoffs", offs)
200 return self.regfile[rnum]
201
202 def dump(self):
203 for i in range(0, len(self), 8):
204 s = []
205 for j in range(8):
206 s.append("%08x" % self[i+j].value)
207 s = ' '.join(s)
208 print("reg", "%2d" % i, s)
209
210
211 class PC:
212 def __init__(self, pc_init=0):
213 self.CIA = SelectableInt(pc_init, 64)
214 self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
215
216 def update_nia(self, is_svp64):
217 increment = 8 if is_svp64 else 4
218 self.NIA = self.CIA + SelectableInt(increment, 64)
219
220 def update(self, namespace, is_svp64):
221 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
222 """
223 self.CIA = namespace['NIA'].narrow(64)
224 self.update_nia(is_svp64)
225 namespace['CIA'] = self.CIA
226 namespace['NIA'] = self.NIA
227
228
229 # Simple-V: see https://libre-soc.org/openpower/sv
230 class SVP64State:
231 def __init__(self, init=0):
232 self.spr = SelectableInt(init, 32)
233 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
234 self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
235 self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
236 self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
237 self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
238 self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
239 self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
240
241
242 # SVP64 ReMap field
243 class SVP64RMFields:
244 def __init__(self, init=0):
245 self.spr = SelectableInt(init, 24)
246 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
247 self.mmode = FieldSelectableInt(self.spr, [0])
248 self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
249 self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
250 self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
251 self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
252 self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
253 self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
254
255
256 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
257 class SVP64PrefixFields:
258 def __init__(self):
259 self.insn = SelectableInt(0, 32)
260 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
261 self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
262 self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
263 rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
264 self.rm = FieldSelectableInt(self.insn, rmfields)
265
266
267 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
268 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
269 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
270
271
272 class SPR(dict):
273 def __init__(self, dec2, initial_sprs={}):
274 self.sd = dec2
275 dict.__init__(self)
276 for key, v in initial_sprs.items():
277 if isinstance(key, SelectableInt):
278 key = key.value
279 key = special_sprs.get(key, key)
280 if isinstance(key, int):
281 info = spr_dict[key]
282 else:
283 info = spr_byname[key]
284 if not isinstance(v, SelectableInt):
285 v = SelectableInt(v, info.length)
286 self[key] = v
287
288 def __getitem__(self, key):
289 print("get spr", key)
290 print("dict", self.items())
291 # if key in special_sprs get the special spr, otherwise return key
292 if isinstance(key, SelectableInt):
293 key = key.value
294 if isinstance(key, int):
295 key = spr_dict[key].SPR
296 key = special_sprs.get(key, key)
297 if key == 'HSRR0': # HACK!
298 key = 'SRR0'
299 if key == 'HSRR1': # HACK!
300 key = 'SRR1'
301 if key in self:
302 res = dict.__getitem__(self, key)
303 else:
304 if isinstance(key, int):
305 info = spr_dict[key]
306 else:
307 info = spr_byname[key]
308 dict.__setitem__(self, key, SelectableInt(0, info.length))
309 res = dict.__getitem__(self, key)
310 print("spr returning", key, res)
311 return res
312
313 def __setitem__(self, key, value):
314 if isinstance(key, SelectableInt):
315 key = key.value
316 if isinstance(key, int):
317 key = spr_dict[key].SPR
318 print("spr key", key)
319 key = special_sprs.get(key, key)
320 if key == 'HSRR0': # HACK!
321 self.__setitem__('SRR0', value)
322 if key == 'HSRR1': # HACK!
323 self.__setitem__('SRR1', value)
324 print("setting spr", key, value)
325 dict.__setitem__(self, key, value)
326
327 def __call__(self, ridx):
328 return self[ridx]
329
330 def get_pdecode_idx_in(dec2, name):
331 op = dec2.dec.op
332 in1_sel = yield op.in1_sel
333 in2_sel = yield op.in2_sel
334 in3_sel = yield op.in3_sel
335 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
336 in1 = yield dec2.e.read_reg1.data
337 in2 = yield dec2.e.read_reg2.data
338 in3 = yield dec2.e.read_reg3.data
339 in1_isvec = yield dec2.in1_isvec
340 in2_isvec = yield dec2.in2_isvec
341 in3_isvec = yield dec2.in3_isvec
342 print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
343 # identify which regnames map to in1/2/3
344 if name == 'RA':
345 if (in1_sel == In1Sel.RA.value or
346 (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
347 return in1, in1_isvec
348 if in1_sel == In1Sel.RA_OR_ZERO.value:
349 return in1, in1_isvec
350 elif name == 'RB':
351 if in2_sel == In2Sel.RB.value:
352 return in2, in2_isvec
353 if in3_sel == In3Sel.RB.value:
354 return in3, in3_isvec
355 # XXX TODO, RC doesn't exist yet!
356 elif name == 'RC':
357 assert False, "RC does not exist yet"
358 elif name == 'RS':
359 if in1_sel == In1Sel.RS.value:
360 return in1, in1_isvec
361 if in2_sel == In2Sel.RS.value:
362 return in2, in2_isvec
363 if in3_sel == In3Sel.RS.value:
364 return in3, in3_isvec
365 return None, False
366
367
368 def get_pdecode_cr_out(dec2, name):
369 op = dec2.dec.op
370 out_sel = yield op.cr_out
371 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
372 out = yield dec2.e.write_cr.data
373 o_isvec = yield dec2.o_isvec
374 print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
375 # identify which regnames map to out / o2
376 if name == 'CR0':
377 if out_sel == CROutSel.CR0.value:
378 return out, o_isvec
379 print ("get_pdecode_idx_out not found", name)
380 return None, False
381
382
383 def get_pdecode_idx_out(dec2, name):
384 op = dec2.dec.op
385 out_sel = yield op.out_sel
386 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
387 out = yield dec2.e.write_reg.data
388 o_isvec = yield dec2.o_isvec
389 print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
390 # identify which regnames map to out / o2
391 if name == 'RA':
392 if out_sel == OutSel.RA.value:
393 return out, o_isvec
394 elif name == 'RT':
395 if out_sel == OutSel.RT.value:
396 return out, o_isvec
397 print ("get_pdecode_idx_out not found", name)
398 return None, False
399
400
401 # XXX TODO
402 def get_pdecode_idx_out2(dec2, name):
403 op = dec2.dec.op
404 print ("TODO: get_pdecode_idx_out2", name)
405 return None, False
406
407
408 class ISACaller:
409 # decoder2 - an instance of power_decoder2
410 # regfile - a list of initial values for the registers
411 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
412 # respect_pc - tracks the program counter. requires initial_insns
413 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
414 initial_mem=None, initial_msr=0,
415 initial_svstate=0,
416 initial_insns=None, respect_pc=False,
417 disassembly=None,
418 initial_pc=0,
419 bigendian=False):
420
421 self.bigendian = bigendian
422 self.halted = False
423 self.is_svp64_mode = False
424 self.respect_pc = respect_pc
425 if initial_sprs is None:
426 initial_sprs = {}
427 if initial_mem is None:
428 initial_mem = {}
429 if initial_insns is None:
430 initial_insns = {}
431 assert self.respect_pc == False, "instructions required to honor pc"
432
433 print("ISACaller insns", respect_pc, initial_insns, disassembly)
434 print("ISACaller initial_msr", initial_msr)
435
436 # "fake program counter" mode (for unit testing)
437 self.fake_pc = 0
438 disasm_start = 0
439 if not respect_pc:
440 if isinstance(initial_mem, tuple):
441 self.fake_pc = initial_mem[0]
442 disasm_start = self.fake_pc
443 else:
444 disasm_start = initial_pc
445
446 # disassembly: we need this for now (not given from the decoder)
447 self.disassembly = {}
448 if disassembly:
449 for i, code in enumerate(disassembly):
450 self.disassembly[i*4 + disasm_start] = code
451
452 # set up registers, instruction memory, data memory, PC, SPRs, MSR
453 self.svp64rm = SVP64RM()
454 if isinstance(initial_svstate, int):
455 initial_svstate = SVP64State(initial_svstate)
456 self.svstate = initial_svstate
457 self.gpr = GPR(decoder2, self, self.svstate, regfile)
458 self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
459 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
460 self.pc = PC()
461 self.spr = SPR(decoder2, initial_sprs)
462 self.msr = SelectableInt(initial_msr, 64) # underlying reg
463
464 # TODO, needed here:
465 # FPR (same as GPR except for FP nums)
466 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
467 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
468 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
469 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
470 # -- Done
471 # 2.3.2 LR (actually SPR #8) -- Done
472 # 2.3.3 CTR (actually SPR #9) -- Done
473 # 2.3.4 TAR (actually SPR #815)
474 # 3.2.2 p45 XER (actually SPR #1) -- Done
475 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
476
477 # create CR then allow portions of it to be "selectable" (below)
478 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
479 self.cr = SelectableInt(initial_cr, 64) # underlying reg
480 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
481
482 # "undefined", just set to variable-bit-width int (use exts "max")
483 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
484
485 self.namespace = {}
486 self.namespace.update(self.spr)
487 self.namespace.update({'GPR': self.gpr,
488 'MEM': self.mem,
489 'SPR': self.spr,
490 'memassign': self.memassign,
491 'NIA': self.pc.NIA,
492 'CIA': self.pc.CIA,
493 'CR': self.cr,
494 'MSR': self.msr,
495 'undefined': undefined,
496 'mode_is_64bit': True,
497 'SO': XER_bits['SO']
498 })
499
500 # update pc to requested start point
501 self.set_pc(initial_pc)
502
503 # field-selectable versions of Condition Register TODO check bitranges?
504 self.crl = []
505 for i in range(8):
506 bits = tuple(range(i*4+32, (i+1)*4+32)) # errr... maybe?
507 _cr = FieldSelectableInt(self.cr, bits)
508 self.crl.append(_cr)
509 self.namespace["CR%d" % i] = _cr
510
511 self.decoder = decoder2.dec
512 self.dec2 = decoder2
513
514 def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
515 print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
516 # store CIA(+4?) in SRR0, set NIA to 0x700
517 # store MSR in SRR1, set MSR to um errr something, have to check spec
518 self.spr['SRR0'].value = self.pc.CIA.value
519 self.spr['SRR1'].value = self.namespace['MSR'].value
520 self.trap_nia = SelectableInt(trap_addr, 64)
521 self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1
522
523 # set exception bits. TODO: this should, based on the address
524 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
525 # bits appropriately. however it turns out that *for now* in all
526 # cases (all trap_addrs) the exact same thing is needed.
527 self.msr[MSRb.IR] = 0
528 self.msr[MSRb.DR] = 0
529 self.msr[MSRb.FE0] = 0
530 self.msr[MSRb.FE1] = 0
531 self.msr[MSRb.EE] = 0
532 self.msr[MSRb.RI] = 0
533 self.msr[MSRb.SF] = 1
534 self.msr[MSRb.TM] = 0
535 self.msr[MSRb.VEC] = 0
536 self.msr[MSRb.VSX] = 0
537 self.msr[MSRb.PR] = 0
538 self.msr[MSRb.FP] = 0
539 self.msr[MSRb.PMM] = 0
540 self.msr[MSRb.TEs] = 0
541 self.msr[MSRb.TEe] = 0
542 self.msr[MSRb.UND] = 0
543 self.msr[MSRb.LE] = 1
544
545 def memassign(self, ea, sz, val):
546 self.mem.memassign(ea, sz, val)
547
548 def prep_namespace(self, formname, op_fields):
549 # TODO: get field names from form in decoder*1* (not decoder2)
550 # decoder2 is hand-created, and decoder1.sigform is auto-generated
551 # from spec
552 # then "yield" fields only from op_fields rather than hard-coded
553 # list, here.
554 fields = self.decoder.sigforms[formname]
555 for name in op_fields:
556 if name == 'spr':
557 sig = getattr(fields, name.upper())
558 else:
559 sig = getattr(fields, name)
560 val = yield sig
561 # these are all opcode fields involved in index-selection of CR,
562 # and need to do "standard" arithmetic. CR[BA+32] for example
563 # would, if using SelectableInt, only be 5-bit.
564 if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
565 self.namespace[name] = val
566 else:
567 self.namespace[name] = SelectableInt(val, sig.width)
568
569 self.namespace['XER'] = self.spr['XER']
570 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
571 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
572
573 def handle_carry_(self, inputs, outputs, already_done):
574 inv_a = yield self.dec2.e.do.invert_in
575 if inv_a:
576 inputs[0] = ~inputs[0]
577
578 imm_ok = yield self.dec2.e.do.imm_data.ok
579 if imm_ok:
580 imm = yield self.dec2.e.do.imm_data.data
581 inputs.append(SelectableInt(imm, 64))
582 assert len(outputs) >= 1
583 print("outputs", repr(outputs))
584 if isinstance(outputs, list) or isinstance(outputs, tuple):
585 output = outputs[0]
586 else:
587 output = outputs
588 gts = []
589 for x in inputs:
590 print("gt input", x, output)
591 gt = (gtu(x, output))
592 gts.append(gt)
593 print(gts)
594 cy = 1 if any(gts) else 0
595 print("CA", cy, gts)
596 if not (1 & already_done):
597 self.spr['XER'][XER_bits['CA']] = cy
598
599 print("inputs", already_done, inputs)
600 # 32 bit carry
601 # ARGH... different for OP_ADD... *sigh*...
602 op = yield self.dec2.e.do.insn_type
603 if op == MicrOp.OP_ADD.value:
604 res32 = (output.value & (1 << 32)) != 0
605 a32 = (inputs[0].value & (1 << 32)) != 0
606 if len(inputs) >= 2:
607 b32 = (inputs[1].value & (1 << 32)) != 0
608 else:
609 b32 = False
610 cy32 = res32 ^ a32 ^ b32
611 print("CA32 ADD", cy32)
612 else:
613 gts = []
614 for x in inputs:
615 print("input", x, output)
616 print(" x[32:64]", x, x[32:64])
617 print(" o[32:64]", output, output[32:64])
618 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
619 gts.append(gt)
620 cy32 = 1 if any(gts) else 0
621 print("CA32", cy32, gts)
622 if not (2 & already_done):
623 self.spr['XER'][XER_bits['CA32']] = cy32
624
625 def handle_overflow(self, inputs, outputs, div_overflow):
626 if hasattr(self.dec2.e.do, "invert_in"):
627 inv_a = yield self.dec2.e.do.invert_in
628 if inv_a:
629 inputs[0] = ~inputs[0]
630
631 imm_ok = yield self.dec2.e.do.imm_data.ok
632 if imm_ok:
633 imm = yield self.dec2.e.do.imm_data.data
634 inputs.append(SelectableInt(imm, 64))
635 assert len(outputs) >= 1
636 print("handle_overflow", inputs, outputs, div_overflow)
637 if len(inputs) < 2 and div_overflow is None:
638 return
639
640 # div overflow is different: it's returned by the pseudo-code
641 # because it's more complex than can be done by analysing the output
642 if div_overflow is not None:
643 ov, ov32 = div_overflow, div_overflow
644 # arithmetic overflow can be done by analysing the input and output
645 elif len(inputs) >= 2:
646 output = outputs[0]
647
648 # OV (64-bit)
649 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
650 output_sgn = exts(output.value, output.bits) < 0
651 ov = 1 if input_sgn[0] == input_sgn[1] and \
652 output_sgn != input_sgn[0] else 0
653
654 # OV (32-bit)
655 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
656 output32_sgn = exts(output.value, 32) < 0
657 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
658 output32_sgn != input32_sgn[0] else 0
659
660 self.spr['XER'][XER_bits['OV']] = ov
661 self.spr['XER'][XER_bits['OV32']] = ov32
662 so = self.spr['XER'][XER_bits['SO']]
663 so = so | ov
664 self.spr['XER'][XER_bits['SO']] = so
665
666 def handle_comparison(self, outputs, cr_idx=0):
667 out = outputs[0]
668 assert isinstance(out, SelectableInt), \
669 "out zero not a SelectableInt %s" % repr(outputs)
670 print("handle_comparison", out.bits, hex(out.value))
671 # TODO - XXX *processor* in 32-bit mode
672 # https://bugs.libre-soc.org/show_bug.cgi?id=424
673 # if is_32bit:
674 # o32 = exts(out.value, 32)
675 # print ("handle_comparison exts 32 bit", hex(o32))
676 out = exts(out.value, out.bits)
677 print("handle_comparison exts", hex(out))
678 zero = SelectableInt(out == 0, 1)
679 positive = SelectableInt(out > 0, 1)
680 negative = SelectableInt(out < 0, 1)
681 SO = self.spr['XER'][XER_bits['SO']]
682 print("handle_comparison SO", SO)
683 cr_field = selectconcat(negative, positive, zero, SO)
684 self.crl[cr_idx].eq(cr_field)
685
686 def set_pc(self, pc_val):
687 self.namespace['NIA'] = SelectableInt(pc_val, 64)
688 self.pc.update(self.namespace, self.is_svp64_mode)
689
690 def setup_one(self):
691 """set up one instruction
692 """
693 if self.respect_pc:
694 pc = self.pc.CIA.value
695 else:
696 pc = self.fake_pc
697 self._pc = pc
698 ins = self.imem.ld(pc, 4, False, True)
699 if ins is None:
700 raise KeyError("no instruction at 0x%x" % pc)
701 print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
702 print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
703
704 yield self.dec2.sv_rm.eq(0)
705 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
706 yield self.dec2.dec.bigendian.eq(self.bigendian)
707 yield self.dec2.state.msr.eq(self.msr.value)
708 yield self.dec2.state.pc.eq(pc)
709 yield self.dec2.state.svstate.eq(self.svstate.spr.value)
710
711 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
712 yield Settle()
713 opcode = yield self.dec2.dec.opcode_in
714 pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
715 pfx.insn.value = opcode
716 major = pfx.major.asint(msb0=True) # MSB0 inversion
717 print ("prefix test: opcode:", major, bin(major),
718 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
719 self.is_svp64_mode = ((major == 0b000001) and
720 pfx.insn[7].value == 0b1 and
721 pfx.insn[9].value == 0b1)
722 self.pc.update_nia(self.is_svp64_mode)
723 if not self.is_svp64_mode:
724 return
725
726 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
727 print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
728 print (" svstate.vl", self.svstate.vl.asint(msb0=True))
729 print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
730 sv_rm = pfx.rm.asint(msb0=True)
731 ins = self.imem.ld(pc+4, 4, False, True)
732 print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
733 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
734 yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix
735 yield Settle()
736
737 def execute_one(self):
738 """execute one instruction
739 """
740 # get the disassembly code for this instruction
741 if self.is_svp64_mode:
742 code = self.disassembly[self._pc+4]
743 print(" svp64 sim-execute", hex(self._pc), code)
744 else:
745 code = self.disassembly[self._pc]
746 print("sim-execute", hex(self._pc), code)
747 opname = code.split(' ')[0]
748 yield from self.call(opname)
749
750 # don't use this except in special circumstances
751 if not self.respect_pc:
752 self.fake_pc += 4
753
754 print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
755
756 def get_assembly_name(self):
757 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
758 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
759 dec_insn = yield self.dec2.e.do.insn
760 asmcode = yield self.dec2.dec.op.asmcode
761 print("get assembly name asmcode", asmcode, hex(dec_insn))
762 asmop = insns.get(asmcode, None)
763 int_op = yield self.dec2.dec.op.internal_op
764
765 # sigh reconstruct the assembly instruction name
766 if hasattr(self.dec2.e.do, "oe"):
767 ov_en = yield self.dec2.e.do.oe.oe
768 ov_ok = yield self.dec2.e.do.oe.ok
769 else:
770 ov_en = False
771 ov_ok = False
772 if hasattr(self.dec2.e.do, "rc"):
773 rc_en = yield self.dec2.e.do.rc.rc
774 rc_ok = yield self.dec2.e.do.rc.ok
775 else:
776 rc_en = False
777 rc_ok = False
778 # grrrr have to special-case MUL op (see DecodeOE)
779 print("ov %d en %d rc %d en %d op %d" %
780 (ov_ok, ov_en, rc_ok, rc_en, int_op))
781 if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
782 print("mul op")
783 if rc_en & rc_ok:
784 asmop += "."
785 else:
786 if not asmop.endswith("."): # don't add "." to "andis."
787 if rc_en & rc_ok:
788 asmop += "."
789 if hasattr(self.dec2.e.do, "lk"):
790 lk = yield self.dec2.e.do.lk
791 if lk:
792 asmop += "l"
793 print("int_op", int_op)
794 if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
795 AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
796 print("AA", AA)
797 if AA:
798 asmop += "a"
799 spr_msb = yield from self.get_spr_msb()
800 if int_op == MicrOp.OP_MFCR.value:
801 if spr_msb:
802 asmop = 'mfocrf'
803 else:
804 asmop = 'mfcr'
805 # XXX TODO: for whatever weird reason this doesn't work
806 # https://bugs.libre-soc.org/show_bug.cgi?id=390
807 if int_op == MicrOp.OP_MTCRF.value:
808 if spr_msb:
809 asmop = 'mtocrf'
810 else:
811 asmop = 'mtcrf'
812 return asmop
813
814 def get_spr_msb(self):
815 dec_insn = yield self.dec2.e.do.insn
816 return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?
817
818 def call(self, name):
819 """call(opcode) - the primary execution point for instructions
820 """
821 name = name.strip() # remove spaces if not already done so
822 if self.halted:
823 print("halted - not executing", name)
824 return
825
826 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
827 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
828 asmop = yield from self.get_assembly_name()
829 print("call", name, asmop)
830
831 # check privileged
832 int_op = yield self.dec2.dec.op.internal_op
833 spr_msb = yield from self.get_spr_msb()
834
835 instr_is_privileged = False
836 if int_op in [MicrOp.OP_ATTN.value,
837 MicrOp.OP_MFMSR.value,
838 MicrOp.OP_MTMSR.value,
839 MicrOp.OP_MTMSRD.value,
840 # TODO: OP_TLBIE
841 MicrOp.OP_RFID.value]:
842 instr_is_privileged = True
843 if int_op in [MicrOp.OP_MFSPR.value,
844 MicrOp.OP_MTSPR.value] and spr_msb:
845 instr_is_privileged = True
846
847 print("is priv", instr_is_privileged, hex(self.msr.value),
848 self.msr[MSRb.PR])
849 # check MSR priv bit and whether op is privileged: if so, throw trap
850 if instr_is_privileged and self.msr[MSRb.PR] == 1:
851 self.TRAP(0x700, PIb.PRIV)
852 self.namespace['NIA'] = self.trap_nia
853 self.pc.update(self.namespace, self.is_svp64_mode)
854 return
855
856 # check halted condition
857 if name == 'attn':
858 self.halted = True
859 return
860
861 # check illegal instruction
862 illegal = False
863 if name not in ['mtcrf', 'mtocrf']:
864 illegal = name != asmop
865
866 if illegal:
867 print("illegal", name, asmop)
868 self.TRAP(0x700, PIb.ILLEG)
869 self.namespace['NIA'] = self.trap_nia
870 self.pc.update(self.namespace, self.is_svp64_mode)
871 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
872 (name, asmop, self.pc.CIA.value))
873 return
874
875 info = self.instrs[name]
876 yield from self.prep_namespace(info.form, info.op_fields)
877
878 # preserve order of register names
879 input_names = create_args(list(info.read_regs) +
880 list(info.uninit_regs))
881 print(input_names)
882
883 # get SVP64 entry for the current instruction
884 sv_rm = self.svp64rm.instrs.get(name)
885 if sv_rm is not None:
886 dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
887 else:
888 dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
889 print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
890
891 # get SVSTATE srcstep. TODO: dststep (twin predication)
892 srcstep = self.svstate.srcstep.asint(msb0=True)
893 vl = self.svstate.vl.asint(msb0=True)
894 mvl = self.svstate.maxvl.asint(msb0=True)
895
896 # VL=0 in SVP64 mode means "do nothing: skip instruction"
897 if self.is_svp64_mode and vl == 0:
898 self.pc.update(self.namespace, self.is_svp64_mode)
899 print("end of call", self.namespace['CIA'], self.namespace['NIA'])
900 return
901
902 # main input registers (RT, RA ...)
903 inputs = []
904 for name in input_names:
905 # using PowerDecoder2, first, find the decoder index.
906 # (mapping name RA RB RC RS to in1, in2, in3)
907 regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
908 if regnum is None:
909 # doing this is not part of svp64, it's because output
910 # registers, to be modified, need to be in the namespace.
911 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
912 # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
913 # XXX already done by PowerDecoder2, now
914 #if is_vec:
915 # regnum += srcstep # TODO, elwidth overrides
916
917 # in case getting the register number is needed, _RA, _RB
918 regname = "_" + name
919 self.namespace[regname] = regnum
920 print('reading reg %s %d' % (name, regnum), is_vec)
921 reg_val = self.gpr(regnum)
922 inputs.append(reg_val)
923
924 # "special" registers
925 for special in info.special_regs:
926 if special in special_sprs:
927 inputs.append(self.spr[special])
928 else:
929 inputs.append(self.namespace[special])
930
931 # clear trap (trap) NIA
932 self.trap_nia = None
933
934 print(inputs)
935 results = info.func(self, *inputs)
936 print(results)
937
938 # "inject" decorator takes namespace from function locals: we need to
939 # overwrite NIA being overwritten (sigh)
940 if self.trap_nia is not None:
941 self.namespace['NIA'] = self.trap_nia
942
943 print("after func", self.namespace['CIA'], self.namespace['NIA'])
944
945 # detect if CA/CA32 already in outputs (sra*, basically)
946 already_done = 0
947 if info.write_regs:
948 output_names = create_args(info.write_regs)
949 for name in output_names:
950 if name == 'CA':
951 already_done |= 1
952 if name == 'CA32':
953 already_done |= 2
954
955 print("carry already done?", bin(already_done))
956 if hasattr(self.dec2.e.do, "output_carry"):
957 carry_en = yield self.dec2.e.do.output_carry
958 else:
959 carry_en = False
960 if carry_en:
961 yield from self.handle_carry_(inputs, results, already_done)
962
963 # detect if overflow was in return result
964 overflow = None
965 if info.write_regs:
966 for name, output in zip(output_names, results):
967 if name == 'overflow':
968 overflow = output
969
970 if hasattr(self.dec2.e.do, "oe"):
971 ov_en = yield self.dec2.e.do.oe.oe
972 ov_ok = yield self.dec2.e.do.oe.ok
973 else:
974 ov_en = False
975 ov_ok = False
976 print("internal overflow", overflow, ov_en, ov_ok)
977 if ov_en & ov_ok:
978 yield from self.handle_overflow(inputs, results, overflow)
979
980 if hasattr(self.dec2.e.do, "rc"):
981 rc_en = yield self.dec2.e.do.rc.rc
982 else:
983 rc_en = False
984 if rc_en:
985 regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
986 regnum = 0 # TODO fix
987 self.handle_comparison(results, regnum)
988
989 # svp64 loop can end early if the dest is scalar
990 svp64_dest_vector = False
991
992 # any modified return results?
993 if info.write_regs:
994 for name, output in zip(output_names, results):
995 if name == 'overflow': # ignore, done already (above)
996 continue
997 if isinstance(output, int):
998 output = SelectableInt(output, 256)
999 if name in ['CA', 'CA32']:
1000 if carry_en:
1001 print("writing %s to XER" % name, output)
1002 self.spr['XER'][XER_bits[name]] = output.value
1003 else:
1004 print("NOT writing %s to XER" % name, output)
1005 elif name in info.special_regs:
1006 print('writing special %s' % name, output, special_sprs)
1007 if name in special_sprs:
1008 self.spr[name] = output
1009 else:
1010 self.namespace[name].eq(output)
1011 if name == 'MSR':
1012 print('msr written', hex(self.msr.value))
1013 else:
1014 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
1015 name)
1016 if regnum is None:
1017 # temporary hack for not having 2nd output
1018 regnum = yield getattr(self.decoder, name)
1019 is_vec = False
1020 # here's where we go "vector".
1021 if is_vec:
1022 # XXX already done by PowerDecoder2
1023 # regnum += srcstep # TODO, elwidth overrides
1024 svp64_dest_vector = True
1025 print('writing reg %d %s' % (regnum, str(output)), is_vec)
1026 if output.bits > 64:
1027 output = SelectableInt(output.value, 64)
1028 self.gpr[regnum] = output
1029
1030 # check if it is the SVSTATE.src/dest step that needs incrementing
1031 # this is our Sub-Program-Counter loop from 0 to VL-1
1032 if self.is_svp64_mode:
1033 # XXX twin predication TODO
1034 vl = self.svstate.vl.asint(msb0=True)
1035 mvl = self.svstate.maxvl.asint(msb0=True)
1036 srcstep = self.svstate.srcstep.asint(msb0=True)
1037 print (" svstate.vl", vl)
1038 print (" svstate.mvl", mvl)
1039 print (" svstate.srcstep", srcstep)
1040 # check if srcstep needs incrementing by one, stop PC advancing
1041 if svp64_dest_vector and srcstep != vl-1:
1042 self.svstate.srcstep += SelectableInt(1, 7)
1043 self.pc.NIA.value = self.pc.CIA.value
1044 self.namespace['NIA'] = self.pc.NIA
1045 print("end of sub-pc call", self.namespace['CIA'],
1046 self.namespace['NIA'])
1047 return # DO NOT allow PC to update whilst Sub-PC loop running
1048 # reset to zero
1049 self.svstate.srcstep[0:7] = 0
1050 print (" svstate.srcstep loop end (PC to update)")
1051 self.pc.update_nia(self.is_svp64_mode)
1052 self.namespace['NIA'] = self.pc.NIA
1053
1054 # UPDATE program counter
1055 self.pc.update(self.namespace, self.is_svp64_mode)
1056 print("end of call", self.namespace['CIA'], self.namespace['NIA'])
1057
1058
1059 def inject():
1060 """Decorator factory.
1061
1062 this decorator will "inject" variables into the function's namespace,
1063 from the *dictionary* in self.namespace. it therefore becomes possible
1064 to make it look like a whole stack of variables which would otherwise
1065 need "self." inserted in front of them (*and* for those variables to be
1066 added to the instance) "appear" in the function.
1067
1068 "self.namespace['SI']" for example becomes accessible as just "SI" but
1069 *only* inside the function, when decorated.
1070 """
1071 def variable_injector(func):
1072 @wraps(func)
1073 def decorator(*args, **kwargs):
1074 try:
1075 func_globals = func.__globals__ # Python 2.6+
1076 except AttributeError:
1077 func_globals = func.func_globals # Earlier versions.
1078
1079 context = args[0].namespace # variables to be injected
1080 saved_values = func_globals.copy() # Shallow copy of dict.
1081 func_globals.update(context)
1082 result = func(*args, **kwargs)
1083 print("globals after", func_globals['CIA'], func_globals['NIA'])
1084 print("args[0]", args[0].namespace['CIA'],
1085 args[0].namespace['NIA'])
1086 args[0].namespace = func_globals
1087 #exec (func.__code__, func_globals)
1088
1089 # finally:
1090 # func_globals = saved_values # Undo changes.
1091
1092 return result
1093
1094 return decorator
1095
1096 return variable_injector