src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from soc.decoder.power_decoder import create_pdecode
  10 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  11                                      LdstLen, In1Sel, In2Sel, In3Sel,
  12                                      OutSel, SPR, RC)
  13
  14
  15 class DecodeA(Elaboratable):
  16     """DecodeA from instruction
  17
  18     decodes register RA, whether immediate-zero, implicit and
  19     explicit CSRs
  20     """
  21
  22     def __init__(self, dec):
  23         self.dec = dec
  24         self.sel_in = Signal(In1Sel, reset_less=True)
  25         self.insn_in = Signal(32, reset_less=True)
  26         self.reg_out = Data(5, name="reg_a")
  27         self.immz_out = Signal(reset_less=True)
  28         self.spr_out = Data(10, "spr_a")
  29
  30     def elaborate(self, platform):
  31         m = Module()
  32         comb = m.d.comb
  33
  34         # select Register A field
  35         ra = Signal(5, reset_less=True)
  36         comb += ra.eq(self.dec.RA)
  37         with m.If((self.sel_in == In1Sel.RA) |
  38                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  39                    (ra != Const(0, 5)))):
  40             comb += self.reg_out.data.eq(ra)
  41             comb += self.reg_out.ok.eq(1)
  42
  43         # zero immediate requested
  44         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  45                   (self.reg_out.data == Const(0, 5))):
  46             comb += self.immz_out.eq(1)
  47
  48         # decode SPR1 based on instruction type
  49         op = self.dec.op
  50         # BC or BCREG: potential implicit register (CTR)
  51         with m.If((op.internal_op == InternalOp.OP_BC) |
  52                   (op.internal_op == InternalOp.OP_BCREG)):
  53             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  54                 comb += self.spr_out.data.eq(SPR.CTR) # constant: CTR
  55                 comb += self.spr_out.ok.eq(1)
  56         # MFSPR or MTSPR: move-from / move-to SPRs
  57         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  58                   (op.internal_op == InternalOp.OP_MTSPR)):
  59             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  60             comb += self.spr_out.ok.eq(1)
  61
  62         return m
  63
  64
  65 class Data(Record):
  66
  67     def __init__(self, width, name):
  68         name_ok = "%s_ok" % name
  69         layout = ((name, width), (name_ok, 1))
  70         Record.__init__(self, layout)
  71         self.data = getattr(self, name) # convenience
  72         self.ok = getattr(self, name_ok) # convenience
  73         self.data.reset_less = True # grrr
  74         self.reset_less = True # grrr
  75
  76     def ports(self):
  77         return [self.data, self.ok]
  78
  79
  80 class DecodeB(Elaboratable):
  81     """DecodeB from instruction
  82
  83     decodes register RB, different forms of immediate (signed, unsigned),
  84     and implicit SPRs
  85     """
  86
  87     def __init__(self, dec):
  88         self.dec = dec
  89         self.sel_in = Signal(In2Sel, reset_less=True)
  90         self.insn_in = Signal(32, reset_less=True)
  91         self.reg_out = Data(5, "reg_b")
  92         self.imm_out = Data(64, "imm_b")
  93         self.spr_out = Data(10, "spr_b")
  94
  95     def exts(self, exts_data, width, fullwidth):
  96         exts_data = exts_data[0:width]
  97         topbit = exts_data[-1]
  98         signbits = Repl(topbit, fullwidth-width)
  99         return Cat(exts_data, signbits)
 100
 101
 102     def elaborate(self, platform):
 103         m = Module()
 104         comb = m.d.comb
 105
 106         # select Register B field
 107         with m.Switch(self.sel_in):
 108             with m.Case(In2Sel.RB):
 109                 comb += self.reg_out.data.eq(self.dec.RB)
 110                 comb += self.reg_out.ok.eq(1)
 111             with m.Case(In2Sel.CONST_UI):
 112                 comb += self.imm_out.data.eq(self.dec.UI)
 113                 comb += self.imm_out.ok.eq(1)
 114             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 115                 comb += self.imm_out.data.eq(
 116                     self.exts(self.dec.SI, 16, 64))
 117                 comb += self.imm_out.ok.eq(1)
 118             with m.Case(In2Sel.CONST_UI_HI):
 119                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 120                 comb += self.imm_out.ok.eq(1)
 121             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 122                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 123                 comb += self.imm_out.data.eq(
 124                     self.exts(self.dec.SI << 16, 32, 64))
 125                 comb += self.imm_out.ok.eq(1)
 126             with m.Case(In2Sel.CONST_LI):
 127                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 128                 comb += self.imm_out.ok.eq(1)
 129             with m.Case(In2Sel.CONST_BD):
 130                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 131                 comb += self.imm_out.ok.eq(1)
 132             with m.Case(In2Sel.CONST_DS):
 133                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 134                 comb += self.imm_out.ok.eq(1)
 135             with m.Case(In2Sel.CONST_M1):
 136                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 137                 comb += self.imm_out.ok.eq(1)
 138             with m.Case(In2Sel.CONST_SH):
 139                 comb += self.imm_out.data.eq(self.dec.sh)
 140                 comb += self.imm_out.ok.eq(1)
 141             with m.Case(In2Sel.CONST_SH32):
 142                 comb += self.imm_out.data.eq(self.dec.SH32)
 143                 comb += self.imm_out.ok.eq(1)
 144
 145         # decode SPR2 based on instruction type
 146         op = self.dec.op
 147         # BCREG implicitly uses CTR or LR for 2nd reg
 148         with m.If(op.internal_op == InternalOp.OP_BCREG):
 149             with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 150                 comb += self.spr_out.data.eq(SPR.CTR)
 151             with m.Else():
 152                 comb += self.spr_out.data.eq(SPR.LR)
 153             comb += self.spr_out.ok.eq(1)
 154
 155         return m
 156
 157
 158 class DecodeC(Elaboratable):
 159     """DecodeC from instruction
 160
 161     decodes register RC
 162     """
 163
 164     def __init__(self, dec):
 165         self.dec = dec
 166         self.sel_in = Signal(In3Sel, reset_less=True)
 167         self.insn_in = Signal(32, reset_less=True)
 168         self.reg_out = Data(5, "reg_c")
 169
 170     def elaborate(self, platform):
 171         m = Module()
 172         comb = m.d.comb
 173
 174         # select Register C field
 175         with m.If(self.sel_in == In3Sel.RS):
 176             comb += self.reg_out.data.eq(self.dec.RS)
 177             comb += self.reg_out.ok.eq(1)
 178
 179         return m
 180
 181
 182 class DecodeOut(Elaboratable):
 183     """DecodeOut from instruction
 184
 185     decodes output register RA, RT or SPR
 186     """
 187
 188     def __init__(self, dec):
 189         self.dec = dec
 190         self.sel_in = Signal(OutSel, reset_less=True)
 191         self.insn_in = Signal(32, reset_less=True)
 192         self.reg_out = Data(5, "reg_o")
 193         self.spr_out = Data(10, "spr_o")
 194
 195     def elaborate(self, platform):
 196         m = Module()
 197         comb = m.d.comb
 198
 199         # select Register out field
 200         with m.Switch(self.sel_in):
 201             with m.Case(OutSel.RT):
 202                 comb += self.reg_out.data.eq(self.dec.RT)
 203                 comb += self.reg_out.ok.eq(1)
 204             with m.Case(OutSel.RA):
 205                 comb += self.reg_out.data.eq(self.dec.RA)
 206                 comb += self.reg_out.ok.eq(1)
 207             with m.Case(OutSel.SPR):
 208                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 209                 comb += self.spr_out.ok.eq(1)
 210
 211         return m
 212
 213
 214 class DecodeRC(Elaboratable):
 215     """DecodeRc from instruction
 216
 217     decodes Record bit Rc
 218     """
 219     def __init__(self, dec):
 220         self.dec = dec
 221         self.sel_in = Signal(RC, reset_less=True)
 222         self.insn_in = Signal(32, reset_less=True)
 223         self.rc_out = Data(1, "rc")
 224
 225     def elaborate(self, platform):
 226         m = Module()
 227         comb = m.d.comb
 228
 229         # select Record bit out field
 230         with m.Switch(self.sel_in):
 231             with m.Case(RC.RC):
 232                 comb += self.rc_out.data.eq(self.dec.Rc)
 233                 comb += self.rc_out.ok.eq(1)
 234             with m.Case(RC.ONE):
 235                 comb += self.rc_out.data.eq(1)
 236                 comb += self.rc_out.ok.eq(1)
 237             with m.Case(RC.NONE):
 238                 comb += self.rc_out.data.eq(0)
 239                 comb += self.rc_out.ok.eq(1)
 240
 241         return m
 242
 243
 244 class DecodeOE(Elaboratable):
 245     """DecodeOE from instruction
 246
 247     decodes OE field: uses RC decode detection which might not be good
 248
 249     -- For now, use "rc" in the decode table to decide whether oe exists.
 250     -- This is not entirely correct architecturally: For mulhd and
 251     -- mulhdu, the OE field is reserved. It remains to be seen what an
 252     -- actual POWER9 does if we set it on those instructions, for now we
 253     -- test that further down when assigning to the multiplier oe input.
 254     """
 255     def __init__(self, dec):
 256         self.dec = dec
 257         self.sel_in = Signal(RC, reset_less=True)
 258         self.insn_in = Signal(32, reset_less=True)
 259         self.oe_out = Data(1, "oe")
 260
 261     def elaborate(self, platform):
 262         m = Module()
 263         comb = m.d.comb
 264
 265         # select OE bit out field
 266         with m.Switch(self.sel_in):
 267             with m.Case(RC.RC):
 268                 comb += self.oe_out.data.eq(self.dec.OE)
 269                 comb += self.oe_out.ok.eq(1)
 270
 271         return m
 272
 273
 274 class XerBits:
 275     def __init__(self):
 276         self.ca = Signal(reset_less=True)
 277         self.ca32 = Signal(reset_less=True)
 278         self.ov = Signal(reset_less=True)
 279         self.ov32 = Signal(reset_less=True)
 280         self.so = Signal(reset_less=True)
 281
 282     def ports(self):
 283         return [self.ca, self.ca32, self.ov, self.ov32, self.so, ]
 284
 285
 286 class Decode2ToExecute1Type:
 287
 288     def __init__(self):
 289
 290         self.valid = Signal(reset_less=True)
 291         self.insn_type = Signal(InternalOp, reset_less=True)
 292         self.nia = Signal(64, reset_less=True)
 293         self.write_reg = Data(5, name="rego")
 294         self.read_reg1 = Data(5, name="reg1")
 295         self.read_reg2 = Data(5, name="reg2")
 296         self.read_reg3 = Data(5, name="reg3")
 297         self.imm_data = Data(64, name="imm")
 298         self.write_spr = Data(10, name="spro")
 299         self.read_spr1 = Data(10, name="spr1")
 300         self.read_spr2 = Data(10, name="spr2")
 301         #self.read_data1 = Signal(64, reset_less=True)
 302         #self.read_data2 = Signal(64, reset_less=True)
 303         #self.read_data3 = Signal(64, reset_less=True)
 304         #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
 305         #self.xerc = XerBits() # NO: this is from the XER SPR
 306         self.lk = Signal(reset_less=True)
 307         self.rc = Data(1, "rc")
 308         self.oe = Data(1, "oe")
 309         self.invert_a = Signal(reset_less=True)
 310         self.invert_out = Signal(reset_less=True)
 311         self.input_carry = Signal(CryIn, reset_less=True)
 312         self.output_carry = Signal(reset_less=True)
 313         self.input_cr = Signal(reset_less=True)
 314         self.output_cr = Signal(reset_less=True)
 315         self.is_32bit = Signal(reset_less=True)
 316         self.is_signed = Signal(reset_less=True)
 317         self.insn = Signal(32, reset_less=True)
 318         self.data_len = Signal(4, reset_less=True) # bytes
 319         self.byte_reverse  = Signal(reset_less=True)
 320         self.sign_extend  = Signal(reset_less=True)# do we need this?
 321         self.update  = Signal(reset_less=True) # is this an update instruction?
 322
 323     def ports(self):
 324         return [self.valid, self.insn_type, self.nia,
 325                 #self.read_data1, self.read_data2, self.read_data3,
 326                 #self.cr,
 327                 self.lk,
 328                 self.invert_a, self.invert_out,
 329                 self.input_carry, self.output_carry,
 330                 self.input_cr, self.output_cr,
 331                 self.is_32bit, self.is_signed,
 332                 self.insn,
 333                 self.data_len, self.byte_reverse , self.sign_extend ,
 334                 self.update] + \
 335                 self.oe.ports() + \
 336                 self.rc.ports() + \
 337                 self.write_spr.ports() + \
 338                 self.read_spr1.ports() + \
 339                 self.read_spr2.ports() + \
 340                 self.write_reg.ports() + \
 341                 self.read_reg1.ports() + \
 342                 self.read_reg2.ports() + \
 343                 self.read_reg3.ports() + \
 344                 self.imm_data.ports()
 345                 # + self.xerc.ports()
 346
 347
 348 class PowerDecode2(Elaboratable):
 349
 350     def __init__(self, dec):
 351
 352         self.dec = dec
 353         self.e = Decode2ToExecute1Type()
 354
 355     def ports(self):
 356         return self.dec.ports() + self.e.ports()
 357
 358     def elaborate(self, platform):
 359         m = Module()
 360         comb = m.d.comb
 361
 362         # set up submodule decoders
 363         m.submodules.dec = self.dec
 364         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 365         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 366         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 367         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 368         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 369         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 370
 371         # copy instruction through...
 372         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 373                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
 374                   dec_oe.insn_in]:
 375             comb += i.eq(self.dec.opcode_in)
 376
 377         # ...and subdecoders' input fields
 378         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 379         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 380         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 381         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 382         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 383         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 384
 385         # decode LD/ST length
 386         with m.Switch(self.dec.op.ldst_len):
 387             with m.Case(LdstLen.is1B):
 388                 comb += self.e.data_len.eq(1)
 389             with m.Case(LdstLen.is2B):
 390                 comb += self.e.data_len.eq(2)
 391             with m.Case(LdstLen.is4B):
 392                 comb += self.e.data_len.eq(4)
 393             with m.Case(LdstLen.is8B):
 394                 comb += self.e.data_len.eq(8)
 395
 396         #comb += self.e.nia.eq(self.dec.nia) # XXX TODO
 397         itype = Mux(self.dec.op.function_unit == Function.NONE,
 398                     InternalOp.OP_ILLEGAL,
 399                     self.dec.op.internal_op)
 400         comb += self.e.insn_type.eq(itype)
 401
 402         # registers a, b, c and out
 403         comb += self.e.read_reg1.eq(dec_a.reg_out)
 404         comb += self.e.read_reg2.eq(dec_b.reg_out)
 405         comb += self.e.read_reg3.eq(dec_c.reg_out)
 406         comb += self.e.write_reg.eq(dec_o.reg_out)
 407         comb += self.e.imm_data.eq(dec_b.imm_out)
 408
 409         # rc and oe out
 410         comb += self.e.rc.eq(dec_rc.rc_out)
 411         comb += self.e.oe.eq(dec_oe.oe_out)
 412
 413         # SPRs out
 414         comb += self.e.read_spr1.eq(dec_a.spr_out)
 415         comb += self.e.read_spr2.eq(dec_b.spr_out)
 416         comb += self.e.write_spr.eq(dec_o.spr_out)
 417
 418         # decoded/selected instruction flags
 419         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 420         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 421         comb += self.e.input_carry.eq(self.dec.op.cry_in)
 422         comb += self.e.output_carry.eq(self.dec.op.cry_out)
 423         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 424         comb += self.e.is_signed.eq(self.dec.op.sgn)
 425         with m.If(self.dec.op.lk):
 426             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 427
 428         comb += self.e.byte_reverse.eq(self.dec.op.br)
 429         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 430         comb += self.e.update.eq(self.dec.op.upd)
 431
 432         comb += self.e.input_cr.eq(self.dec.op.cr_in)
 433         comb += self.e.output_cr.eq(self.dec.op.cr_out)
 434
 435
 436         return m
 437
 438
 439 if __name__ == '__main__':
 440     pdecode = create_pdecode()
 441     dec2 = PowerDecode2(pdecode)
 442     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 443     with open("dec2.il", "w") as f:
 444         f.write(vl)
 445