src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21
  22 def instr_is_privileged(m, op, insn):
  23     """determines if the instruction is privileged or not
  24     """
  25     comb = m.d.comb
  26     Signal = is_priv_insn(reset_less=True)
  27     with m.Switch(op):
  28         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
  29         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
  30         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
  31         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
  32         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  33     with m.If(op == OP_MFSPR | op == OP_MTSPR):
  34         with m.If(insn[20]): # field XFX.spr[-1] i think
  35             comb += is_priv_insn.eq(1)
  36     return is_priv_insn
  37
  38
  39 class DecodeA(Elaboratable):
  40     """DecodeA from instruction
  41
  42     decodes register RA, whether immediate-zero, implicit and
  43     explicit CSRs
  44     """
  45
  46     def __init__(self, dec):
  47         self.dec = dec
  48         self.sel_in = Signal(In1Sel, reset_less=True)
  49         self.insn_in = Signal(32, reset_less=True)
  50         self.reg_out = Data(5, name="reg_a")
  51         self.immz_out = Signal(reset_less=True)
  52         self.spr_out = Data(10, "spr_a")
  53         self.fast_out = Data(3, "fast_a")
  54
  55     def elaborate(self, platform):
  56         m = Module()
  57         comb = m.d.comb
  58
  59         # select Register A field
  60         ra = Signal(5, reset_less=True)
  61         comb += ra.eq(self.dec.RA)
  62         with m.If((self.sel_in == In1Sel.RA) |
  63                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  64                    (ra != Const(0, 5)))):
  65             comb += self.reg_out.data.eq(ra)
  66             comb += self.reg_out.ok.eq(1)
  67
  68         # zero immediate requested
  69         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  70                   (self.reg_out.data == Const(0, 5))):
  71             comb += self.immz_out.eq(1)
  72
  73         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  74         with m.If(self.sel_in == In1Sel.RS):
  75             comb += self.reg_out.data.eq(self.dec.RS)
  76             comb += self.reg_out.ok.eq(1)
  77
  78         # decode Fast-SPR based on instruction type
  79         op = self.dec.op
  80         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  81         with m.If(op.internal_op == InternalOp.OP_BC):
  82             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  83                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  84                 comb += self.fast_out.ok.eq(1)
  85         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  86             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  87             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
  88             with m.If(xo9 & ~xo5):
  89                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  90                 comb += self.fast_out.ok.eq(1)
  91
  92         # MFSPR move from SPRs
  93         with m.If(op.internal_op == InternalOp.OP_MFSPR):
  94             # XXX TODO: fast/slow SPR decoding and mapping
  95             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  96             comb += self.spr_out.ok.eq(1)
  97
  98         return m
  99
 100
 101 class Data(Record):
 102
 103     def __init__(self, width, name):
 104         name_ok = "%s_ok" % name
 105         layout = ((name, width), (name_ok, 1))
 106         Record.__init__(self, layout)
 107         self.data = getattr(self, name) # convenience
 108         self.ok = getattr(self, name_ok) # convenience
 109         self.data.reset_less = True # grrr
 110         self.reset_less = True # grrr
 111
 112     def ports(self):
 113         return [self.data, self.ok]
 114
 115
 116 class DecodeB(Elaboratable):
 117     """DecodeB from instruction
 118
 119     decodes register RB, different forms of immediate (signed, unsigned),
 120     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 121     by industry-standard convention, "lane 2" is where fully-decoded
 122     immediates are muxed in.
 123     """
 124
 125     def __init__(self, dec):
 126         self.dec = dec
 127         self.sel_in = Signal(In2Sel, reset_less=True)
 128         self.insn_in = Signal(32, reset_less=True)
 129         self.reg_out = Data(5, "reg_b")
 130         self.imm_out = Data(64, "imm_b")
 131         self.fast_out = Data(3, "fast_b")
 132
 133     def elaborate(self, platform):
 134         m = Module()
 135         comb = m.d.comb
 136
 137         # select Register B field
 138         with m.Switch(self.sel_in):
 139             with m.Case(In2Sel.RB):
 140                 comb += self.reg_out.data.eq(self.dec.RB)
 141                 comb += self.reg_out.ok.eq(1)
 142             with m.Case(In2Sel.RS):
 143                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 144                 comb += self.reg_out.ok.eq(1)
 145             with m.Case(In2Sel.CONST_UI):
 146                 comb += self.imm_out.data.eq(self.dec.UI)
 147                 comb += self.imm_out.ok.eq(1)
 148             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 149                 comb += self.imm_out.data.eq(
 150                     exts(self.dec.SI, 16, 64))
 151                 comb += self.imm_out.ok.eq(1)
 152             with m.Case(In2Sel.CONST_UI_HI):
 153                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 154                 comb += self.imm_out.ok.eq(1)
 155             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 156                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 157                 comb += self.imm_out.data.eq(
 158                     exts(self.dec.SI << 16, 32, 64))
 159                 comb += self.imm_out.ok.eq(1)
 160             with m.Case(In2Sel.CONST_LI):
 161                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 162                 comb += self.imm_out.ok.eq(1)
 163             with m.Case(In2Sel.CONST_BD):
 164                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 165                 comb += self.imm_out.ok.eq(1)
 166             with m.Case(In2Sel.CONST_DS):
 167                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 168                 comb += self.imm_out.ok.eq(1)
 169             with m.Case(In2Sel.CONST_M1):
 170                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 171                 comb += self.imm_out.ok.eq(1)
 172             with m.Case(In2Sel.CONST_SH):
 173                 comb += self.imm_out.data.eq(self.dec.sh)
 174                 comb += self.imm_out.ok.eq(1)
 175             with m.Case(In2Sel.CONST_SH32):
 176                 comb += self.imm_out.data.eq(self.dec.SH32)
 177                 comb += self.imm_out.ok.eq(1)
 178
 179         # decode SPR2 based on instruction type
 180         op = self.dec.op
 181         # BCREG implicitly uses LR or TAR for 2nd reg
 182         # CTR however is already in fast_spr1 *not* 2.
 183         with m.If(op.internal_op == InternalOp.OP_BCREG):
 184             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 185             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 186             with m.If(~xo9):
 187                 comb += self.fast_out.data.eq(FastRegs.LR)
 188                 comb += self.fast_out.ok.eq(1)
 189             with m.Elif(xo5):
 190                 comb += self.fast_out.data.eq(FastRegs.TAR)
 191                 comb += self.fast_out.ok.eq(1)
 192
 193         return m
 194
 195
 196 class DecodeC(Elaboratable):
 197     """DecodeC from instruction
 198
 199     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 200     """
 201
 202     def __init__(self, dec):
 203         self.dec = dec
 204         self.sel_in = Signal(In3Sel, reset_less=True)
 205         self.insn_in = Signal(32, reset_less=True)
 206         self.reg_out = Data(5, "reg_c")
 207
 208     def elaborate(self, platform):
 209         m = Module()
 210         comb = m.d.comb
 211
 212         # select Register C field
 213         with m.Switch(self.sel_in):
 214             with m.Case(In3Sel.RB):
 215                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 216                 comb += self.reg_out.ok.eq(1)
 217             with m.Case(In3Sel.RS):
 218                 comb += self.reg_out.data.eq(self.dec.RS)
 219                 comb += self.reg_out.ok.eq(1)
 220
 221         return m
 222
 223
 224 class DecodeOut(Elaboratable):
 225     """DecodeOut from instruction
 226
 227     decodes output register RA, RT or SPR
 228     """
 229
 230     def __init__(self, dec):
 231         self.dec = dec
 232         self.sel_in = Signal(OutSel, reset_less=True)
 233         self.insn_in = Signal(32, reset_less=True)
 234         self.reg_out = Data(5, "reg_o")
 235         self.spr_out = Data(10, "spr_o")
 236         self.fast_out = Data(3, "fast_o")
 237
 238     def elaborate(self, platform):
 239         m = Module()
 240         comb = m.d.comb
 241         op = self.dec.op
 242
 243         # select Register out field
 244         with m.Switch(self.sel_in):
 245             with m.Case(OutSel.RT):
 246                 comb += self.reg_out.data.eq(self.dec.RT)
 247                 comb += self.reg_out.ok.eq(1)
 248             with m.Case(OutSel.RA):
 249                 comb += self.reg_out.data.eq(self.dec.RA)
 250                 comb += self.reg_out.ok.eq(1)
 251             with m.Case(OutSel.SPR):
 252                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 253                 comb += self.spr_out.ok.eq(1)
 254                 # TODO MTSPR 1st spr (fast)
 255                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 256                     pass
 257                     """
 258                     sprn := decode_spr_num(f_in.insn);
 259                     v.ispr1 := fast_spr_num(sprn);
 260                     -- Make slow SPRs single issue
 261                     if is_fast_spr(v.ispr1) = '0' then
 262                         v.decode.sgl_pipe := '1';
 263                         -- send MMU-related SPRs to loadstore1
 264                         case sprn is
 265                         when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
 266                             v.decode.unit := LDST;
 267                         when others =>
 268                         end case;
 269                     end if;
 270                     """
 271
 272
 273         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 274         op = self.dec.op
 275         with m.If((op.internal_op == InternalOp.OP_BC) |
 276                   (op.internal_op == InternalOp.OP_BCREG)):
 277             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 278                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 279                 comb += self.fast_out.ok.eq(1)
 280
 281         # RFID 1st spr (fast)
 282         with m.If(op.internal_op == InternalOp.OP_RFID):
 283             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 284             comb += self.fast_out.ok.eq(1)
 285
 286         return m
 287
 288
 289 class DecodeOut2(Elaboratable):
 290     """DecodeOut2 from instruction
 291
 292     decodes output registers
 293     """
 294
 295     def __init__(self, dec):
 296         self.dec = dec
 297         self.sel_in = Signal(OutSel, reset_less=True)
 298         self.lk = Signal(reset_less=True)
 299         self.insn_in = Signal(32, reset_less=True)
 300         self.reg_out = Data(5, "reg_o")
 301         self.fast_out = Data(3, "fast_o")
 302
 303     def elaborate(self, platform):
 304         m = Module()
 305         comb = m.d.comb
 306
 307         # update mode LD/ST uses read-reg A also as an output
 308         with m.If(self.dec.op.upd):
 309             comb += self.reg_out.eq(self.dec.RA)
 310             comb += self.reg_out.ok.eq(1)
 311
 312         # BC or BCREG: potential implicit register (LR) output
 313         op = self.dec.op
 314         with m.If((op.internal_op == InternalOp.OP_BC) |
 315                   (op.internal_op == InternalOp.OP_BCREG)):
 316             with m.If(self.lk): # "link" mode
 317                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 318                 comb += self.fast_out.ok.eq(1)
 319
 320         # RFID 2nd spr (fast)
 321         with m.If(op.internal_op == InternalOp.OP_RFID):
 322                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 323                 comb += self.fast_out.ok.eq(1)
 324
 325         return m
 326
 327
 328 class DecodeRC(Elaboratable):
 329     """DecodeRc from instruction
 330
 331     decodes Record bit Rc
 332     """
 333     def __init__(self, dec):
 334         self.dec = dec
 335         self.sel_in = Signal(RC, reset_less=True)
 336         self.insn_in = Signal(32, reset_less=True)
 337         self.rc_out = Data(1, "rc")
 338
 339     def elaborate(self, platform):
 340         m = Module()
 341         comb = m.d.comb
 342
 343         # select Record bit out field
 344         with m.Switch(self.sel_in):
 345             with m.Case(RC.RC):
 346                 comb += self.rc_out.data.eq(self.dec.Rc)
 347                 comb += self.rc_out.ok.eq(1)
 348             with m.Case(RC.ONE):
 349                 comb += self.rc_out.data.eq(1)
 350                 comb += self.rc_out.ok.eq(1)
 351             with m.Case(RC.NONE):
 352                 comb += self.rc_out.data.eq(0)
 353                 comb += self.rc_out.ok.eq(1)
 354
 355         return m
 356
 357
 358 class DecodeOE(Elaboratable):
 359     """DecodeOE from instruction
 360
 361     decodes OE field: uses RC decode detection which might not be good
 362
 363     -- For now, use "rc" in the decode table to decide whether oe exists.
 364     -- This is not entirely correct architecturally: For mulhd and
 365     -- mulhdu, the OE field is reserved. It remains to be seen what an
 366     -- actual POWER9 does if we set it on those instructions, for now we
 367     -- test that further down when assigning to the multiplier oe input.
 368     """
 369     def __init__(self, dec):
 370         self.dec = dec
 371         self.sel_in = Signal(RC, reset_less=True)
 372         self.insn_in = Signal(32, reset_less=True)
 373         self.oe_out = Data(1, "oe")
 374
 375     def elaborate(self, platform):
 376         m = Module()
 377         comb = m.d.comb
 378
 379         # select OE bit out field
 380         with m.Switch(self.sel_in):
 381             with m.Case(RC.RC):
 382                 comb += self.oe_out.data.eq(self.dec.OE)
 383                 comb += self.oe_out.ok.eq(1)
 384
 385         return m
 386
 387 class DecodeCRIn(Elaboratable):
 388     """Decodes input CR from instruction
 389
 390     CR indices - insn fields - (not the data *in* the CR) require only 3
 391     bits because they refer to CR0-CR7
 392     """
 393
 394     def __init__(self, dec):
 395         self.dec = dec
 396         self.sel_in = Signal(CRInSel, reset_less=True)
 397         self.insn_in = Signal(32, reset_less=True)
 398         self.cr_bitfield = Data(3, "cr_bitfield")
 399         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 400         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 401         self.whole_reg = Signal(reset_less=True)
 402
 403     def elaborate(self, platform):
 404         m = Module()
 405         comb = m.d.comb
 406
 407         comb += self.cr_bitfield.ok.eq(0)
 408         comb += self.cr_bitfield_b.ok.eq(0)
 409         comb += self.whole_reg.eq(0)
 410         with m.Switch(self.sel_in):
 411             with m.Case(CRInSel.NONE):
 412                 pass # No bitfield activated
 413             with m.Case(CRInSel.CR0):
 414                 comb += self.cr_bitfield.data.eq(0)
 415                 comb += self.cr_bitfield.ok.eq(1)
 416             with m.Case(CRInSel.BI):
 417                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 418                 comb += self.cr_bitfield.ok.eq(1)
 419             with m.Case(CRInSel.BFA):
 420                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 421                 comb += self.cr_bitfield.ok.eq(1)
 422             with m.Case(CRInSel.BA_BB):
 423                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 424                 comb += self.cr_bitfield.ok.eq(1)
 425                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 426                 comb += self.cr_bitfield_b.ok.eq(1)
 427                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 428                 comb += self.cr_bitfield_o.ok.eq(1)
 429             with m.Case(CRInSel.BC):
 430                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 431                 comb += self.cr_bitfield.ok.eq(1)
 432             with m.Case(CRInSel.WHOLE_REG):
 433                 comb += self.whole_reg.eq(1)
 434
 435         return m
 436
 437
 438 class DecodeCROut(Elaboratable):
 439     """Decodes input CR from instruction
 440
 441     CR indices - insn fields - (not the data *in* the CR) require only 3
 442     bits because they refer to CR0-CR7
 443     """
 444
 445     def __init__(self, dec):
 446         self.dec = dec
 447         self.rc_in = Signal(reset_less=True)
 448         self.sel_in = Signal(CROutSel, reset_less=True)
 449         self.insn_in = Signal(32, reset_less=True)
 450         self.cr_bitfield = Data(3, "cr_bitfield")
 451         self.whole_reg = Signal(reset_less=True)
 452
 453     def elaborate(self, platform):
 454         m = Module()
 455         comb = m.d.comb
 456
 457         comb += self.cr_bitfield.ok.eq(0)
 458         comb += self.whole_reg.eq(0)
 459         with m.Switch(self.sel_in):
 460             with m.Case(CROutSel.NONE):
 461                 pass # No bitfield activated
 462             with m.Case(CROutSel.CR0):
 463                 comb += self.cr_bitfield.data.eq(0)
 464                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 465             with m.Case(CROutSel.BF):
 466                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 467                 comb += self.cr_bitfield.ok.eq(1)
 468             with m.Case(CROutSel.BT):
 469                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 470                 comb += self.cr_bitfield.ok.eq(1)
 471             with m.Case(CROutSel.WHOLE_REG):
 472                 comb += self.whole_reg.eq(1)
 473
 474         return m
 475
 476
 477 class XerBits:
 478     def __init__(self):
 479         self.ca = Signal(2, reset_less=True)
 480         self.ov = Signal(2, reset_less=True)
 481         self.so = Signal(reset_less=True)
 482
 483     def ports(self):
 484         return [self.ca, self.ov, self.so]
 485
 486
 487 class Decode2ToExecute1Type(RecordObject):
 488
 489     def __init__(self, name=None):
 490
 491         RecordObject.__init__(self, name=name)
 492
 493         self.valid = Signal(reset_less=True)
 494         self.insn_type = Signal(InternalOp, reset_less=True)
 495         self.fn_unit = Signal(Function, reset_less=True)
 496         self.nia = Signal(64, reset_less=True)
 497         self.write_reg = Data(5, name="rego")
 498         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 499         self.read_reg1 = Data(5, name="reg1")
 500         self.read_reg2 = Data(5, name="reg2")
 501         self.read_reg3 = Data(5, name="reg3")
 502         self.imm_data = Data(64, name="imm")
 503         self.write_spr = Data(10, name="spro")
 504         self.read_spr1 = Data(10, name="spr1")
 505         self.read_spr2 = Data(10, name="spr2")
 506
 507         self.read_fast1 = Data(3, name="fast1")
 508         self.read_fast2 = Data(3, name="fast2")
 509         self.write_fast1 = Data(3, name="fasto1")
 510         self.write_fast2 = Data(3, name="fasto2")
 511
 512         self.read_cr1 = Data(3, name="cr_in1")
 513         self.read_cr2 = Data(3, name="cr_in2")
 514         self.read_cr3 = Data(3, name="cr_in2")
 515         self.read_cr_whole = Signal(reset_less=True)
 516         self.write_cr = Data(3, name="cr_out")
 517         self.write_cr_whole = Signal(reset_less=True)
 518         self.lk = Signal(reset_less=True)
 519         self.rc = Data(1, "rc")
 520         self.oe = Data(1, "oe")
 521         self.invert_a = Signal(reset_less=True)
 522         self.zero_a = Signal(reset_less=True)
 523         self.invert_out = Signal(reset_less=True)
 524         self.input_carry = Signal(CryIn, reset_less=True)
 525         self.output_carry = Signal(reset_less=True)
 526         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 527         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 528         self.is_32bit = Signal(reset_less=True)
 529         self.is_signed = Signal(reset_less=True)
 530         self.insn = Signal(32, reset_less=True)
 531         self.data_len = Signal(4, reset_less=True) # bytes
 532         self.byte_reverse  = Signal(reset_less=True)
 533         self.sign_extend  = Signal(reset_less=True)# do we need this?
 534         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 535
 536
 537 class PowerDecode2(Elaboratable):
 538
 539     def __init__(self, dec):
 540
 541         self.dec = dec
 542         self.e = Decode2ToExecute1Type()
 543
 544     def ports(self):
 545         return self.dec.ports() + self.e.ports()
 546
 547     def elaborate(self, platform):
 548         m = Module()
 549         comb = m.d.comb
 550         e, op = self.e, self.dec.op
 551
 552         # set up submodule decoders
 553         m.submodules.dec = self.dec
 554         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 555         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 556         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 557         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 558         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 559         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 560         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 561         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 562         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 563
 564         # copy instruction through...
 565         for i in [e.insn, dec_a.insn_in, dec_b.insn_in,
 566                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 567                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 568             comb += i.eq(self.dec.opcode_in)
 569
 570         # ...and subdecoders' input fields
 571         comb += dec_a.sel_in.eq(op.in1_sel)
 572         comb += dec_b.sel_in.eq(op.in2_sel)
 573         comb += dec_c.sel_in.eq(op.in3_sel)
 574         comb += dec_o.sel_in.eq(op.out_sel)
 575         comb += dec_o2.sel_in.eq(op.out_sel)
 576         comb += dec_o2.lk.eq(e.lk)
 577         comb += dec_rc.sel_in.eq(op.rc_sel)
 578         comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
 579         comb += dec_cr_in.sel_in.eq(op.cr_in)
 580         comb += dec_cr_out.sel_in.eq(op.cr_out)
 581         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 582
 583         # decode LD/ST length
 584         with m.Switch(op.ldst_len):
 585             with m.Case(LdstLen.is1B):
 586                 comb += e.data_len.eq(1)
 587             with m.Case(LdstLen.is2B):
 588                 comb += e.data_len.eq(2)
 589             with m.Case(LdstLen.is4B):
 590                 comb += e.data_len.eq(4)
 591             with m.Case(LdstLen.is8B):
 592                 comb += e.data_len.eq(8)
 593
 594         comb += e.nia.eq(0)    # XXX TODO (or remove? not sure yet)
 595         fu = op.function_unit
 596         itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op)
 597         comb += e.insn_type.eq(itype)
 598         comb += e.fn_unit.eq(fu)
 599
 600         # registers a, b, c and out and out2 (LD/ST EA)
 601         comb += e.read_reg1.eq(dec_a.reg_out)
 602         comb += e.read_reg2.eq(dec_b.reg_out)
 603         comb += e.read_reg3.eq(dec_c.reg_out)
 604         comb += e.write_reg.eq(dec_o.reg_out)
 605         comb += e.write_ea.eq(dec_o2.reg_out)
 606         comb += e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 607         comb += e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 608
 609         # rc and oe out
 610         comb += e.rc.eq(dec_rc.rc_out)
 611         comb += e.oe.eq(dec_oe.oe_out)
 612
 613         # SPRs out
 614         comb += e.read_spr1.eq(dec_a.spr_out)
 615         comb += e.write_spr.eq(dec_o.spr_out)
 616
 617         # Fast regs out
 618         comb += e.read_fast1.eq(dec_a.fast_out)
 619         comb += e.read_fast2.eq(dec_b.fast_out)
 620         comb += e.write_fast1.eq(dec_o.fast_out)
 621         comb += e.write_fast2.eq(dec_o2.fast_out)
 622
 623         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 624         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 625         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 626         comb += e.read_cr_whole.eq(dec_cr_in.whole_reg)
 627
 628         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 629         comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
 630
 631         # decoded/selected instruction flags
 632         comb += e.invert_a.eq(op.inv_a)
 633         comb += e.invert_out.eq(op.inv_out)
 634         comb += e.input_carry.eq(op.cry_in)   # carry comes in
 635         comb += e.output_carry.eq(op.cry_out) # carry goes out
 636         comb += e.is_32bit.eq(op.is_32b)
 637         comb += e.is_signed.eq(op.sgn)
 638         with m.If(op.lk):
 639             comb += e.lk.eq(self.dec.LK) # XXX TODO: accessor
 640
 641         comb += e.byte_reverse.eq(op.br)
 642         comb += e.sign_extend.eq(op.sgn_ext)
 643         comb += e.update.eq(op.upd) # LD/ST "update" mode.
 644
 645
 646         # These should be removed eventually
 647         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
 648         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 649
 650
 651         return m
 652
 653     def regspecmap(self, regfile, regname):
 654         """regspecmap: provides PowerDecode2 with an encoding relationship
 655         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 656         regfile and regname arguments are fields 1 and 2 from a given regspec.
 657         """
 658         return regspec_decode(self.e, regfile, regname)
 659
 660     def rdflags(self, cu):
 661         rdl = []
 662         for idx in range(cu.n_src):
 663             regfile, regname, _ = cu.get_in_spec(idx)
 664             rdflag, read, write = self.regspecmap(regfile, regname)
 665             rdl.append(rdflag)
 666         print ("rdflags", rdl)
 667         return Cat(*rdl)
 668
 669
 670 if __name__ == '__main__':
 671     pdecode = create_pdecode()
 672     dec2 = PowerDecode2(pdecode)
 673     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 674     with open("dec2.il", "w") as f:
 675         f.write(vl)
 676