1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Mux
, Elaboratable
5 from nmutil
.latch
import SRLatch
, latchregister
6 from soc
.decoder
.power_decoder2
import Data
7 from soc
.decoder
.power_enums
import InternalOp
9 from soc
.experiment
.alu_hier
import CompALUOpSubset
11 """ Computation Unit (aka "ALU Manager").
13 This module runs a "revolving door" set of three latches, based on
17 where one of them cannot be set on any given cycle.
18 (Note however that opc_l has been inverted (and qn used), due to SRLatch
19 default reset state being "0" rather than "1")
21 * When issue is first raised, a busy signal is sent out.
22 The src1 and src2 registers and the operand can be latched in
25 * Read request is set, which is acknowledged through the Scoreboard
26 to the priority picker, which generates (one and only one) Go_Read
27 at a time. One of those will (eventually) be this Computation Unit.
29 * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
30 src1/src2/operand in place), and the ALU is told to proceed.
32 * As this is currently a "demo" unit, a countdown timer is activated
33 to simulate an ALU "pipeline", which activates "write request release",
34 and the ALU's output is captured into a temporary register.
36 * Write request release will go through a similar process as Read request,
37 resulting (eventually) in Go_Write being asserted.
39 * When Go_Write is asserted, two things happen: (1) the data in the temp
40 register is placed combinatorially onto the output, and (2) the
41 req_l latch is cleared, busy is dropped, and the Comp Unit is back
42 through its revolving door to do another task.
46 class ComputationUnitNoDelay(Elaboratable
):
47 def __init__(self
, rwid
, alu
):
49 self
.alu
= alu
# actual ALU - set as a "submodule" of the CU
51 self
.counter
= Signal(4)
52 self
.go_rd_i
= Signal(reset_less
=True) # go read in
53 self
.go_wr_i
= Signal(reset_less
=True) # go write in
54 self
.issue_i
= Signal(reset_less
=True) # fn issue in
55 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
56 self
.go_die_i
= Signal() # go die (reset)
58 # operation / data input
59 self
.oper_i
= CompALUOpSubset() # operand
60 self
.src1_i
= Signal(rwid
, reset_less
=True) # oper1 in
61 self
.src2_i
= Signal(rwid
, reset_less
=True) # oper2 in
63 self
.busy_o
= Signal(reset_less
=True) # fn busy out
64 self
.data_o
= Signal(rwid
, reset_less
=True) # Dest out
65 self
.rd_rel_o
= Signal(reset_less
=True) # release src1/src2 request
66 # release request out (valid_o)
67 self
.req_rel_o
= Signal(reset_less
=True)
68 self
.done_o
= self
.req_rel_o
# 'normalise' API
70 def elaborate(self
, platform
):
72 m
.submodules
.alu
= self
.alu
73 m
.submodules
.src_l
= src_l
= SRLatch(sync
=False, name
="src")
74 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
75 m
.submodules
.req_l
= req_l
= SRLatch(sync
=False, name
="req")
78 reset_w
= Signal(reset_less
=True)
79 reset_r
= Signal(reset_less
=True)
80 m
.d
.comb
+= reset_w
.eq(self
.go_wr_i | self
.go_die_i
)
81 m
.d
.comb
+= reset_r
.eq(self
.go_rd_i | self
.go_die_i
)
83 # This is fascinating and very important to observe that this
84 # is in effect a "3-way revolving door". At no time may all 3
85 # latches be set at the same time.
87 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
88 m
.d
.sync
+= opc_l
.s
.eq(self
.issue_i
) # XXX NOTE: INVERTED FROM book!
89 m
.d
.sync
+= opc_l
.r
.eq(reset_w
) # XXX NOTE: INVERTED FROM book!
91 # src operand latch (not using go_wr_i)
92 m
.d
.sync
+= src_l
.s
.eq(self
.issue_i
)
93 m
.d
.sync
+= src_l
.r
.eq(reset_r
)
95 # dest operand latch (not using issue_i)
96 m
.d
.sync
+= req_l
.s
.eq(self
.go_rd_i
)
97 m
.d
.sync
+= req_l
.r
.eq(reset_w
)
99 # create a latch/register for the operand
100 oper_r
= CompALUOpSubset()
101 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, "oper_l")
103 # and one for the output from the ALU
104 data_r
= Signal(self
.rwid
, reset_less
=True) # Dest register
105 latchregister(m
, self
.alu
.o
, data_r
, req_l
.q
, "data_l")
107 # pass the operation to the ALU
108 m
.d
.comb
+= self
.alu
.op
.eq(oper_r
)
110 # select immediate if opcode says so. however also change the latch
111 # to trigger *from* the opcode latch instead.
112 op_is_imm
= oper_r
.imm_data
.imm_ok
113 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
114 src_sel
= Signal(reset_less
=True)
115 m
.d
.comb
+= src_sel
.eq(Mux(op_is_imm
, opc_l
.q
, src_l
.q
))
116 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
,
119 # create a latch/register for src1/src2
120 latchregister(m
, self
.src1_i
, self
.alu
.a
, src_l
.q
)
121 latchregister(m
, src2_or_imm
, self
.alu
.b
, src_sel
)
127 # all request signals gated by busy_o. prevents picker problems
129 m
.d
.comb
+= busy_o
.eq(opc_l
.q
) # busy out
130 m
.d
.comb
+= self
.rd_rel_o
.eq(src_l
.q
& busy_o
) # src1/src2 req rel
132 # on a go_read, tell the ALU we're accepting data.
133 # NOTE: this spells TROUBLE if the ALU isn't ready!
134 # go_read is only valid for one clock!
135 with m
.If(self
.go_rd_i
): # src operands ready, GO!
136 with m
.If(~self
.alu
.p_ready_o
): # no ACK yet
137 m
.d
.comb
+= self
.alu
.p_valid_i
.eq(1) # so indicate valid
139 # only proceed if ALU says its output is valid
140 with m
.If(self
.alu
.n_valid_o
):
141 # when ALU ready, write req release out. waits for shadow
142 m
.d
.comb
+= self
.req_rel_o
.eq(req_l
.q
& busy_o
& self
.shadown_i
)
143 # when output latch is ready, and ALU says ready, accept ALU output
144 with m
.If(self
.req_rel_o
& self
.go_wr_i
):
145 # tells ALU "thanks got it"
146 m
.d
.comb
+= self
.alu
.n_ready_i
.eq(1)
148 # output the data from the latch on go_write
149 with m
.If(self
.go_wr_i
):
150 m
.d
.comb
+= self
.data_o
.eq(data_r
)
160 yield from self
.oper_i
.ports()
172 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0):
173 yield dut
.issue_i
.eq(0)
175 yield dut
.src1_i
.eq(a
)
176 yield dut
.src2_i
.eq(b
)
177 yield dut
.oper_i
.insn_type
.eq(op
)
178 yield dut
.oper_i
.invert_a
.eq(inv_a
)
179 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
180 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
181 yield dut
.issue_i
.eq(1)
183 yield dut
.issue_i
.eq(0)
185 yield dut
.go_rd_i
.eq(1)
188 rd_rel_o
= yield dut
.rd_rel_o
189 print("rd_rel", rd_rel_o
)
193 yield dut
.go_rd_i
.eq(0)
194 req_rel_o
= yield dut
.req_rel_o
195 result
= yield dut
.data_o
196 print("req_rel", req_rel_o
, result
)
198 req_rel_o
= yield dut
.req_rel_o
199 result
= yield dut
.data_o
200 print("req_rel", req_rel_o
, result
)
204 yield dut
.go_wr_i
.eq(1)
206 result
= yield dut
.data_o
207 print("result", result
)
208 yield dut
.go_wr_i
.eq(0)
213 def scoreboard_sim(dut
):
214 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=0,
218 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=1)
219 assert result
== 65532
221 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
)
225 def test_scoreboard():
226 from alu_hier
import ALU
227 from soc
.decoder
.power_decoder2
import Decode2ToExecute1Type
230 dut
= ComputationUnitNoDelay(16, alu
)
231 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
232 with
open("test_compalu.il", "w") as f
:
235 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_compalu.vcd')
238 if __name__
== '__main__':