src/soc/experiment/compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from nmigen.compat.sim import run_simulation, Settle
  14 from nmigen.cli import verilog, rtlil
  15 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const
  16 from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT)
  17
  18 from nmutil.latch import SRLatch, latchregister
  19 from nmutil.iocontrol import RecordObject
  20
  21 from soc.decoder.power_decoder2 import Data
  22 from soc.decoder.power_enums import InternalOp
  23 from soc.fu.regspec import RegSpec, RegSpecALUAPI
  24
  25
  26 def go_record(n, name):
  27     r = Record([('go', n, DIR_FANIN),
  28                 ('rel', n, DIR_FANOUT)], name=name)
  29     r.go.reset_less = True
  30     r.rel.reset_less = True
  31     return r
  32
  33 # see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  34
  35 class CompUnitRecord(RegSpec, RecordObject):
  36     """CompUnitRecord
  37
  38     base class for Computation Units, to provide a uniform API
  39     and allow "record.connect" etc. to be used, particularly when
  40     it comes to connecting multiple Computation Units up as a block
  41     (very laborious)
  42
  43     LDSTCompUnitRecord should derive from this class and add the
  44     additional signals it requires
  45
  46     :subkls:      the class (not an instance) needed to construct the opcode
  47     :rwid:        either an integer (specifies width of all regs) or a "regspec"
  48
  49     see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  50     """
  51     def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
  52         RegSpec.__init__(self, rwid, n_src, n_dst)
  53         RecordObject.__init__(self, name)
  54         self._subkls = subkls
  55         n_src, n_dst = self._n_src, self._n_dst
  56
  57         # create source operands
  58         src = []
  59         for i in range(n_src):
  60             j = i + 1 # name numbering to match src1/src2
  61             name = "src%d_i" % j
  62             rw = self._get_srcwid(i)
  63             sreg = Signal(rw, name=name, reset_less=True)
  64             setattr(self, name, sreg)
  65             src.append(sreg)
  66         self._src_i = src
  67
  68         # create dest operands
  69         dst = []
  70         for i in range(n_dst):
  71             j = i + 1 # name numbering to match dest1/2...
  72             name = "dest%d_o" % j
  73             rw = self._get_dstwid(i)
  74             dreg = Signal(rw, name=name, reset_less=True)
  75             setattr(self, name, dreg)
  76             dst.append(dreg)
  77         self._dest = dst
  78
  79         # operation / data input
  80         self.oper_i = subkls(name="oper_i") # operand
  81
  82         # create read/write and other scoreboard signalling
  83         self.rd = go_record(n_src, name="rd") # read in, req out
  84         self.wr = go_record(n_dst, name="wr") # write in, req out
  85         self.issue_i = Signal(reset_less=True) # fn issue in
  86         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  87         self.go_die_i = Signal() # go die (reset)
  88
  89         # output (busy/done)
  90         self.busy_o = Signal(reset_less=True) # fn busy out
  91         self.done_o = Signal(reset_less=True)
  92
  93
  94 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
  95     def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1):
  96         """MultiCompUnit
  97
  98         * :rwid:        width of register latches (TODO: allocate per regspec)
  99         * :alu:         ALU (pipeline, FSM) - must conform to nmutil Pipe API
 100         * :opsubsetkls: subset of Decode2ExecuteType
 101         * :n_src:       number of src operands
 102         * :n_dst:       number of destination operands
 103         """
 104         RegSpecALUAPI.__init__(self, rwid, alu)
 105         self.opsubsetkls = opsubsetkls
 106         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst)
 107         n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst
 108         print ("n_src %d n_dst %d" % (self.n_src, self.n_dst))
 109
 110         # convenience names for src operands
 111         for i in range(n_src):
 112             j = i + 1 # name numbering to match src1/src2
 113             name = "src%d_i" % j
 114             setattr(self, name, getattr(cu, name))
 115
 116         # convenience names for dest operands
 117         for i in range(n_dst):
 118             j = i + 1 # name numbering to match dest1/2...
 119             name = "dest%d_o" % j
 120             setattr(self, name, getattr(cu, name))
 121
 122         # more convenience names
 123         self.rd = cu.rd
 124         self.wr = cu.wr
 125         self.go_rd_i = self.rd.go # temporary naming
 126         self.go_wr_i = self.wr.go # temporary naming
 127         self.rd_rel_o = self.rd.rel # temporary naming
 128         self.req_rel_o = self.wr.rel # temporary naming
 129         self.issue_i = cu.issue_i
 130         self.shadown_i = cu.shadown_i
 131         self.go_die_i = cu.go_die_i
 132
 133         # operation / data input
 134         self.oper_i = cu.oper_i
 135         self.src_i = cu._src_i
 136
 137         self.busy_o = cu.busy_o
 138         self.dest = cu._dest
 139         self.data_o = self.dest[0] # Dest out
 140         self.done_o = cu.done_o
 141
 142
 143     def _mux_op(self, m, sl, op_is_imm, imm, i):
 144         # select imm if opcode says so. however also change the latch
 145         # to trigger *from* the opcode latch instead.
 146         src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
 147         src_sel = Signal(reset_less=True)
 148         m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
 149         m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
 150         # overwrite 1st src-latch with immediate-muxed stuff
 151         sl[i][0] = src_or_imm
 152         sl[i][2] = src_sel
 153         sl[i][3] = ~op_is_imm # change rd.rel[i] gate condition
 154
 155     def elaborate(self, platform):
 156         m = Module()
 157         m.submodules.alu = self.alu
 158         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 159         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 160         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
 161         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 162         m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
 163         self.opc_l, self.src_l = opc_l, src_l
 164
 165         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
 166         # so combine it with go_rd_i.  if all bits are set we're good
 167         all_rd = Signal(reset_less=True)
 168         m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
 169                     (((~self.rd.rel) | self.rd.go).all()))
 170
 171         # write_requests all done
 172         # req_done works because any one of the last of the writes
 173         # is enough, when combined with when read-phase is done (rst_l.q)
 174         wr_any = Signal(reset_less=True)
 175         req_done = Signal(reset_less=True)
 176         m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel.bool()))
 177         m.d.comb += wr_any.eq(self.wr.go.bool())
 178         m.d.comb += req_done.eq(rst_l.q & wr_any)
 179
 180         # create rising pulse from alu valid condition.
 181         alu_done = Signal(reset_less=True)
 182         alu_done_dly = Signal(reset_less=True)
 183         alu_pulse = Signal(reset_less=True)
 184         alu_pulsem = Signal(self.n_dst, reset_less=True)
 185         m.d.comb += alu_done.eq(self.alu.n.valid_o)
 186         m.d.sync += alu_done_dly.eq(alu_done)
 187         m.d.comb += alu_pulse.eq(alu_done & ~alu_done_dly)
 188         m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
 189
 190         # shadow/go_die
 191         reset = Signal(reset_less=True)
 192         rst_r = Signal(reset_less=True) # reset latch off
 193         reset_w = Signal(self.n_dst, reset_less=True)
 194         reset_r = Signal(self.n_src, reset_less=True)
 195         m.d.comb += reset.eq(req_done | self.go_die_i)
 196         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
 197         m.d.comb += reset_w.eq(self.wr.go | Repl(self.go_die_i, self.n_dst))
 198         m.d.comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 199
 200         # read-done,wr-proceed latch
 201         m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
 202         m.d.comb += rok_l.r.eq(self.alu.n.valid_o) # off when ALU acknowledges
 203
 204         # wr-done, back-to-start latch
 205         m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
 206         m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
 207
 208         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
 209         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
 210         m.d.sync += opc_l.r.eq(self.alu.n.valid_o & req_done) # reset on ALU
 211
 212         # src operand latch (not using go_wr_i)
 213         m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
 214         m.d.sync += src_l.r.eq(reset_r)
 215
 216         # dest operand latch (not using issue_i)
 217         m.d.comb += req_l.s.eq(alu_pulsem)
 218         m.d.sync += req_l.r.eq(reset_w)
 219
 220         # create a latch/register for the operand
 221         oper_r = self.opsubsetkls(name="oper_r")
 222         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 223
 224         # and for each output from the ALU: capture when ALU output is valid
 225         drl = []
 226         for i in range(self.n_dst):
 227             name = "data_r%d" % i
 228             data_r = Signal(self.cu._get_dstwid(i), name=name, reset_less=True)
 229             latchregister(m, self.get_out(i), data_r, alu_pulsem, name + "_l")
 230             drl.append(data_r)
 231
 232         # pass the operation to the ALU
 233         m.d.comb += self.get_op().eq(oper_r)
 234
 235         # create list of src/alu-src/src-latch.  override 1st and 2nd one below.
 236         # in the case, for ALU and Logical pipelines, we assume RB is the
 237         # 2nd operand in the input "regspec".  see for example
 238         # soc.fu.alu.pipe_data.ALUInputData
 239         sl = []
 240         print ("src_i", self.src_i)
 241         for i in range(self.n_src):
 242             sl.append([self.src_i[i], self.get_in(i), src_l.q[i], Const(1,1)])
 243
 244         # if the operand subset has "zero_a" we implicitly assume that means
 245         # src_i[0] is an INT reg type where zero can be multiplexed in, instead.
 246         # see https://bugs.libre-soc.org/show_bug.cgi?id=336
 247         if hasattr(oper_r, "zero_a"):
 248             # select zero imm if opcode says so.  however also change the latch
 249             # to trigger *from* the opcode latch instead.
 250             self._mux_op(m, sl, oper_r.zero_a, 0, 0)
 251
 252         # if the operand subset has "imm_data" we implicitly assume that means
 253         # "this is an INT ALU/Logical FU jobbie, RB is muxed with the immediate"
 254         if hasattr(oper_r, "imm_data"):
 255             # select immediate if opcode says so. however also change the latch
 256             # to trigger *from* the opcode latch instead.
 257             op_is_imm = oper_r.imm_data.imm_ok
 258             imm = oper_r.imm_data.imm
 259             self._mux_op(m, sl, op_is_imm, imm, 1)
 260
 261         # create a latch/register for src1/src2 (even if it is a copy of imm)
 262         for i in range(self.n_src):
 263             src, alusrc, latch, _ = sl[i]
 264             latchregister(m, src, alusrc, latch, name="src_r%d" % i)
 265
 266         # -----
 267         # outputs
 268         # -----
 269
 270         slg = Cat(*map(lambda x: x[3], sl)) # get req gate conditions
 271         # all request signals gated by busy_o.  prevents picker problems
 272         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 273         bro = Repl(self.busy_o, self.n_src)
 274         m.d.comb += self.rd.rel.eq(src_l.q & bro & slg) # src1/src2 req rel
 275
 276         # write-release gated by busy and by shadow
 277         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
 278         m.d.comb += self.wr.rel.eq(req_l.q & brd)
 279
 280         # generate read-done pulse
 281         all_rd_dly = Signal(reset_less=True)
 282         all_rd_pulse = Signal(reset_less=True)
 283         m.d.sync += all_rd_dly.eq(all_rd)
 284         m.d.comb += all_rd_pulse.eq(all_rd & ~all_rd_dly)
 285
 286         # on a go_read, tell the ALU we're accepting data.
 287         m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
 288         m.d.comb += self.alu.p.valid_i.eq(alui_l.q)
 289         m.d.sync += alui_l.r.eq(self.alu.p.ready_o & alui_l.q)
 290         m.d.comb += alui_l.s.eq(all_rd_pulse)
 291
 292         # ALU output "ready" side.  alu "ready" indication stays hi until
 293         # ALU says "valid".
 294         m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
 295         m.d.comb += self.alu.n.ready_i.eq(alu_l.qn)
 296         m.d.sync += alu_l.r.eq(self.alu.n.valid_o & alu_l.q)
 297         m.d.comb += alu_l.s.eq(all_rd_pulse)
 298
 299         # output the data from the latch on go_write
 300         for i in range(self.n_dst):
 301             with m.If(self.wr.go[i]):
 302                 m.d.comb += self.dest[i].eq(drl[i])
 303
 304         return m
 305
 306     def __iter__(self):
 307         yield self.rd.go
 308         yield self.wr.go
 309         yield self.issue_i
 310         yield self.shadown_i
 311         yield self.go_die_i
 312         yield from self.oper_i.ports()
 313         yield self.src1_i
 314         yield self.src2_i
 315         yield self.busy_o
 316         yield self.rd.rel
 317         yield self.wr.rel
 318         yield self.data_o
 319
 320     def ports(self):
 321         return list(self)
 322
 323
 324 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 325     yield dut.issue_i.eq(0)
 326     yield
 327     yield dut.src_i[0].eq(a)
 328     yield dut.src_i[1].eq(b)
 329     yield dut.oper_i.insn_type.eq(op)
 330     yield dut.oper_i.invert_a.eq(inv_a)
 331     yield dut.oper_i.imm_data.imm.eq(imm)
 332     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 333     yield dut.oper_i.zero_a.eq(zero_a)
 334     yield dut.issue_i.eq(1)
 335     yield
 336     yield dut.issue_i.eq(0)
 337     yield
 338     if not imm_ok or not zero_a:
 339         yield dut.rd.go.eq(0b11)
 340         while True:
 341             yield
 342             rd_rel_o = yield dut.rd.rel
 343             print ("rd_rel", rd_rel_o)
 344             if rd_rel_o:
 345                 break
 346         yield dut.rd.go.eq(0)
 347     if len(dut.src_i) == 3:
 348         yield dut.rd.go.eq(0b100)
 349         while True:
 350             yield
 351             rd_rel_o = yield dut.rd.rel
 352             print ("rd_rel", rd_rel_o)
 353             if rd_rel_o:
 354                 break
 355         yield dut.rd.go.eq(0)
 356
 357     req_rel_o = yield dut.wr.rel
 358     result = yield dut.data_o
 359     print ("req_rel", req_rel_o, result)
 360     while True:
 361         req_rel_o = yield dut.wr.rel
 362         result = yield dut.data_o
 363         print ("req_rel", req_rel_o, result)
 364         if req_rel_o:
 365             break
 366         yield
 367     yield dut.wr.go[0].eq(1)
 368     yield
 369     result = yield dut.data_o
 370     print ("result", result)
 371     yield dut.wr.go[0].eq(0)
 372     yield
 373     return result
 374
 375
 376 def scoreboard_sim_dummy(dut):
 377     result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
 378                                     imm=8, imm_ok=1)
 379     assert result == 5, result
 380
 381     result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
 382                                     imm=8, imm_ok=1)
 383     assert result == 9, result
 384
 385
 386 def scoreboard_sim(dut):
 387     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
 388                                     imm=8, imm_ok=1)
 389     assert result == 13
 390
 391     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
 392     assert result == 7
 393
 394     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
 395     assert result == 65532
 396
 397     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
 398                                     imm=8, imm_ok=1)
 399     assert result == 8
 400
 401     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
 402     assert result == 2
 403
 404
 405 def test_compunit():
 406     from alu_hier import ALU
 407     from soc.fu.alu.alu_input_record import CompALUOpSubset
 408
 409     m = Module()
 410     alu = ALU(16)
 411     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 412     m.submodules.cu = dut
 413
 414     vl = rtlil.convert(dut, ports=dut.ports())
 415     with open("test_compunit1.il", "w") as f:
 416         f.write(vl)
 417
 418     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
 419
 420
 421 class CompUnitParallelTest:
 422     def __init__(self, dut):
 423         self.dut = dut
 424
 425         # Operation cycle should not take longer than this:
 426         self.MAX_BUSY_WAIT = 50
 427
 428         # Minimum duration in which issue_i will be kept inactive,
 429         # during which busy_o must remain low.
 430         self.MIN_BUSY_LOW = 5
 431
 432         # Number of cycles to stall until the assertion of go.
 433         # One value, for each port. Can be zero, for no delay.
 434         self.RD_GO_DELAY = [0, 3]
 435
 436         # store common data for the input operation of the processes
 437         # input operation:
 438         self.op = 0
 439         self.inv_a = self.zero_a = 0
 440         self.imm = self.imm_ok = 0
 441         # input data:
 442         self.a = self.b = 0
 443
 444     def driver(self):
 445         print("Begin parallel test.")
 446         yield from self.operation(5, 2, InternalOp.OP_ADD, inv_a=0,
 447                                   imm=8, imm_ok=1)
 448
 449     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 450         # store data for the operation
 451         self.a = a
 452         self.b = b
 453         self.op = op
 454         self.inv_a = inv_a
 455         self.imm = imm
 456         self.imm_ok = imm_ok
 457         self.zero_a = zero_a
 458
 459         # trigger operation cycle
 460         yield from self.issue()
 461
 462     def issue(self):
 463         # issue_i starts inactive
 464         yield self.dut.issue_i.eq(0)
 465
 466         for n in range(self.MIN_BUSY_LOW):
 467             yield
 468             # busy_o must remain inactive. It cannot rise on its own.
 469             busy_o = yield self.dut.busy_o
 470             assert not busy_o
 471
 472         # activate issue_i to begin the operation cycle
 473         yield self.dut.issue_i.eq(1)
 474
 475         # at the same time, present the operation
 476         yield self.dut.oper_i.insn_type.eq(self.op)
 477         yield self.dut.oper_i.invert_a.eq(self.inv_a)
 478         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
 479         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
 480         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 481
 482         # give one cycle for the CompUnit to latch the data
 483         yield
 484
 485         # busy_o must keep being low in this cycle, because issue_i was
 486         # low on the previous cycle.
 487         # It cannot rise on its own.
 488         # Also, busy_o and issue_i must never be active at the same time, ever.
 489         busy_o = yield self.dut.busy_o
 490         assert not busy_o
 491
 492         # Lower issue_i
 493         yield self.dut.issue_i.eq(0)
 494
 495         # deactivate inputs along with issue_i, so we can be sure the data
 496         # was latched at the correct cycle
 497         yield self.dut.oper_i.insn_type.eq(0)
 498         yield self.dut.oper_i.invert_a.eq(0)
 499         yield self.dut.oper_i.imm_data.imm.eq(0)
 500         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
 501         yield self.dut.oper_i.zero_a.eq(0)
 502         yield
 503
 504         # wait for busy_o to lower
 505         # timeout after self.MAX_BUSY_WAIT cycles
 506         for n in range(self.MAX_BUSY_WAIT):
 507             # sample busy_o in the current cycle
 508             busy_o = yield self.dut.busy_o
 509             if not busy_o:
 510                 # operation cycle ends when busy_o becomes inactive
 511                 break
 512             yield
 513
 514         # if busy_o is still active, a timeout has occurred
 515         # TODO: Uncomment this, once the test is complete:
 516         # assert not busy_o
 517
 518         if busy_o:
 519             print("If you are reading this, "
 520                   "it's because the above test failed, as expected,\n"
 521                   "with a timeout. It must pass, once the test is complete.")
 522             return
 523
 524         print("If you are reading this, "
 525               "it's because the above test unexpectedly passed.")
 526
 527     def rd(self, rd_idx):
 528         # wait for issue_i to rise
 529         while True:
 530             issue_i = yield self.dut.issue_i
 531             if issue_i:
 532                 break
 533             # issue_i has not risen yet, so rd must keep low
 534             rel = yield self.dut.rd.rel[rd_idx]
 535             assert not rel
 536             yield
 537
 538         # we do not want rd to rise on an immediate operand
 539         # if it is immediate, exit the process
 540         # TODO: don't exit the process, monitor rd instead to ensure it
 541         #       doesn't rise on its own
 542         if (self.zero_a and rd_idx == 0) or (self.imm_ok and rd_idx == 1):
 543             return
 544
 545         # issue_i has risen. rel must rise on the next cycle
 546         rel = yield self.dut.rd.rel[rd_idx]
 547         assert not rel
 548
 549         # stall for additional cycles. Check that rel doesn't fall on its own
 550         for n in range(self.RD_GO_DELAY[rd_idx]):
 551             yield
 552             rel = yield self.dut.rd.rel[rd_idx]
 553             assert rel
 554
 555         # Before asserting "go", make sure "rel" has risen.
 556         # The use of Settle allows "go" to be set combinatorially,
 557         # rising on the same cycle as "rel".
 558         yield Settle()
 559         rel = yield self.dut.rd.rel[rd_idx]
 560         assert rel
 561
 562         # assert go for one cycle
 563         yield self.dut.rd.go[rd_idx].eq(1)
 564         yield
 565
 566         # rel must keep high, since go was inactive in the last cycle
 567         rel = yield self.dut.rd.rel[rd_idx]
 568         assert rel
 569
 570         # finish the go one-clock pulse
 571         yield self.dut.rd.go[rd_idx].eq(0)
 572         yield
 573
 574         # rel must have gone low in response to go being high
 575         # on the previous cycle
 576         rel = yield self.dut.rd.rel[rd_idx]
 577         assert not rel
 578
 579         # TODO: also when dut.rd.go is set, put the expected value into
 580         # the src_i.  use dut.get_in[rd_idx] to do so
 581
 582     def wr(self, wr_idx):
 583         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 584         yield
 585         # TODO: also when dut.wr.go is set, check the output against the
 586         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 587
 588     def run_simulation(self, vcd_name):
 589         run_simulation(self.dut, [self.driver(),
 590                                   self.rd(0),  # one read port (a)
 591                                   self.rd(1),  # one read port (b)
 592                                   self.wr(0),  # one write port (o)
 593                                   ],
 594                        vcd_name=vcd_name)
 595
 596
 597 def test_compunit_regspec3():
 598     from alu_hier import DummyALU
 599     from soc.fu.alu.alu_input_record import CompALUOpSubset
 600
 601     inspec = [('INT', 'a', '0:15'),
 602               ('INT', 'b', '0:15'),
 603               ('INT', 'c', '0:15')]
 604     outspec = [('INT', 'o', '0:15'),
 605               ]
 606
 607     regspec = (inspec, outspec)
 608
 609     m = Module()
 610     alu = DummyALU(16)
 611     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 612     m.submodules.cu = dut
 613
 614     run_simulation(m, scoreboard_sim_dummy(dut),
 615                    vcd_name='test_compunit_regspec3.vcd')
 616
 617
 618 def test_compunit_regspec1():
 619     from alu_hier import ALU
 620     from soc.fu.alu.alu_input_record import CompALUOpSubset
 621
 622     inspec = [('INT', 'a', '0:15'),
 623               ('INT', 'b', '0:15')]
 624     outspec = [('INT', 'o', '0:15'),
 625               ]
 626
 627     regspec = (inspec, outspec)
 628
 629     m = Module()
 630     alu = ALU(16)
 631     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 632     m.submodules.cu = dut
 633
 634     vl = rtlil.convert(dut, ports=dut.ports())
 635     with open("test_compunit_regspec1.il", "w") as f:
 636         f.write(vl)
 637
 638     run_simulation(m, scoreboard_sim(dut),
 639                    vcd_name='test_compunit_regspec1.vcd')
 640
 641     test = CompUnitParallelTest(dut)
 642     test.run_simulation("test_compunit_parallel.vcd")
 643
 644
 645 if __name__ == '__main__':
 646     test_compunit()
 647     test_compunit_regspec1()
 648     test_compunit_regspec3()