3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
, Settle
19 from nmigen
.cli
import rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Cat
, Const
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
24 from nmutil
.latch
import SRLatch
, latchregister
25 from nmutil
.util
import rising_edge
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.scoreboard
.addr_match
import LenExpand
29 # for testing purposes
30 from soc
.experiment
.testmem
import TestMemory
31 #from soc.scoreboard.addr_split import LDSTSplitter
37 class PortInterface(RecordObject
):
40 defines the interface - the API - that the LDSTCompUnit connects
41 to. note that this is NOT a "fire-and-forget" interface. the
42 LDSTCompUnit *must* be kept appraised that the request is in
43 progress, and only when it has a 100% successful completion
44 can the notification be given (busy dropped).
46 The interface FSM rules are as follows:
48 * if busy_o is asserted, a LD/ST is in progress. further
49 requests may not be made until busy_o is deasserted.
51 * only one of is_ld_i or is_st_i may be asserted. busy_o
52 will immediately be asserted and remain asserted.
54 * addr.ok is to be asserted when the LD/ST address is known.
55 addr.data is to be valid on the same cycle.
57 addr.ok and addr.data must REMAIN asserted until busy_o
58 is de-asserted. this ensures that there is no need
59 for the L0 Cache/Buffer to have an additional address latch
60 (because the LDSTCompUnit already has it)
62 * addr_ok_o (or addr_exc_o) must be waited for. these will
63 be asserted *only* for one cycle and one cycle only.
65 * addr_exc_o will be asserted if there is no chance that the
66 memory request may be fulfilled.
68 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
70 * conversely: addr_ok_o must *ONLY* be asserted if there is a
71 HUNDRED PERCENT guarantee that the memory request will be
74 * for a LD, ld.ok will be asserted - for only one clock cycle -
75 at any point in the future that is acceptable to the underlying
76 Memory subsystem. the recipient MUST latch ld.data on that cycle.
78 busy_o is deasserted on the same cycle as ld.ok is asserted.
80 * for a ST, st.ok may be asserted only after addr_ok_o had been
81 asserted, alongside valid st.data at the same time. st.ok
82 must only be asserted for one cycle.
84 the underlying Memory is REQUIRED to pick up that data and
85 guarantee its delivery. no back-acknowledgement is required.
87 busy_o is deasserted on the cycle AFTER st.ok is asserted.
90 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
93 self
._addrwid
= addrwid
95 RecordObject
.__init
__(self
, name
=name
)
97 # distinguish op type (ld/st)
98 self
.is_ld_i
= Signal(reset_less
=True)
99 self
.is_st_i
= Signal(reset_less
=True)
101 # LD/ST data length (TODO: other things may be needed)
102 self
.data_len
= Signal(4, reset_less
=True)
105 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
106 self
.go_die_i
= Signal(reset_less
=True) # back to reset
107 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
108 # addr is valid (TLB, L1 etc.)
109 self
.addr_ok_o
= Signal(reset_less
=True)
110 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
113 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
114 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
116 def connect_port(self
, inport
):
117 print("connect_port", self
, inport
)
118 return [self
.is_ld_i
.eq(inport
.is_ld_i
),
119 self
.is_st_i
.eq(inport
.is_st_i
),
120 self
.data_len
.eq(inport
.data_len
),
121 self
.go_die_i
.eq(inport
.go_die_i
),
122 self
.addr
.data
.eq(inport
.addr
.data
),
123 self
.addr
.ok
.eq(inport
.addr
.ok
),
124 self
.st
.eq(inport
.st
),
125 inport
.ld
.eq(self
.ld
),
126 inport
.busy_o
.eq(self
.busy_o
),
127 inport
.addr_ok_o
.eq(self
.addr_ok_o
),
128 inport
.addr_exc_o
.eq(self
.addr_exc_o
),
132 class PortInterfaceBase(Elaboratable
):
135 Base class for PortInterface-compliant Memory read/writers
138 def __init__(self
, regwid
=64, addrwid
=4):
140 self
.addrwid
= addrwid
141 self
.pi
= PortInterface("ldst_port0", regwid
, addrwid
)
145 return log2_int(self
.regwid
//8)
147 def splitaddr(self
, addr
):
148 """split the address into top and bottom bits of the memory granularity
150 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
152 def connect_port(self
, inport
):
153 return self
.pi
.connect_port(inport
)
155 def set_wr_addr(self
, m
, addr
, mask
): pass
156 def set_rd_addr(self
, m
, addr
, mask
): pass
157 def set_wr_data(self
, m
, data
, wen
): pass
158 def get_rd_data(self
, m
): pass
160 def elaborate(self
, platform
):
162 comb
, sync
= m
.d
.comb
, m
.d
.sync
164 # state-machine latches
165 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
166 m
.submodules
.st_done
= st_done
= SRLatch(False, name
="st_done")
167 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
168 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
169 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
170 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
171 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
175 sync
+= st_done
.s
.eq(0)
176 comb
+= st_done
.r
.eq(0)
177 comb
+= st_active
.r
.eq(0)
178 comb
+= ld_active
.r
.eq(0)
179 comb
+= cyc_l
.s
.eq(0)
180 comb
+= cyc_l
.r
.eq(0)
181 comb
+= busy_l
.s
.eq(0)
182 comb
+= busy_l
.r
.eq(0)
183 sync
+= adrok_l
.s
.eq(0)
184 comb
+= adrok_l
.r
.eq(0)
186 # expand ld/st binary length/addr[:3] into unary bitmap
187 m
.submodules
.lenexp
= lenexp
= LenExpand(4, 8)
189 lds
= Signal(reset_less
=True)
190 sts
= Signal(reset_less
=True)
192 comb
+= lds
.eq(pi
.is_ld_i
) # ld-req signals
193 comb
+= sts
.eq(pi
.is_st_i
) # st-req signals
196 busy_delay
= Signal()
198 sync
+= busy_delay
.eq(pi
.busy_o
)
199 comb
+= busy_edge
.eq(pi
.busy_o
& ~busy_delay
)
201 # activate mode: only on "edge"
202 comb
+= ld_active
.s
.eq(rising_edge(m
, lds
)) # activate LD mode
203 comb
+= st_active
.s
.eq(rising_edge(m
, sts
)) # activate ST mode
205 # LD/ST requested activates "busy" (only if not already busy)
206 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
207 comb
+= busy_l
.s
.eq(~busy_delay
)
209 # if now in "LD" mode: wait for addr_ok, then send the address out
210 # to memory, acknowledge address, and send out LD data
211 with m
.If(ld_active
.q
):
212 # set up LenExpander with the LD len and lower bits of addr
213 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
214 comb
+= lenexp
.len_i
.eq(pi
.data_len
)
215 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
216 with m
.If(pi
.addr
.ok
& adrok_l
.qn
):
217 self
.set_rd_addr(m
, pi
.addr
.data
, lenexp
.lexp_o
)
218 comb
+= pi
.addr_ok_o
.eq(1) # acknowledge addr ok
219 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
221 # if now in "ST" mode: likewise do the same but with "ST"
222 # to memory, acknowledge address, and send out LD data
223 with m
.If(st_active
.q
):
224 # set up LenExpander with the ST len and lower bits of addr
225 lsbaddr
, msbaddr
= self
.splitaddr(pi
.addr
.data
)
226 comb
+= lenexp
.len_i
.eq(pi
.data_len
)
227 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
228 with m
.If(pi
.addr
.ok
):
229 self
.set_wr_addr(m
, pi
.addr
.data
, lenexp
.lexp_o
)
230 with m
.If(adrok_l
.qn
):
231 comb
+= pi
.addr_ok_o
.eq(1) # acknowledge addr ok
232 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
234 # for LD mode, when addr has been "ok'd", assume that (because this
235 # is a "Memory" test-class) the memory read data is valid.
236 comb
+= reset_l
.s
.eq(0)
237 comb
+= reset_l
.r
.eq(0)
238 lddata
= Signal(self
.regwid
, reset_less
=True)
239 data
, ldok
= self
.get_rd_data(m
)
240 comb
+= lddata
.eq((data
& lenexp
.rexp_o
) >>
242 with m
.If(ld_active
.q
& adrok_l
.q
):
243 # shift data down before pushing out. requires masking
244 # from the *byte*-expanded version of LenExpand output
245 comb
+= pi
.ld
.data
.eq(lddata
) # put data out
246 comb
+= pi
.ld
.ok
.eq(ldok
) # indicate data valid
247 comb
+= reset_l
.s
.eq(ldok
) # reset mode after 1 cycle
249 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
250 with m
.If(st_active
.q
& pi
.st
.ok
):
251 # shift data up before storing. lenexp *bit* version of mask is
252 # passed straight through as byte-level "write-enable" lines.
253 stdata
= Signal(self
.regwid
, reset_less
=True)
254 comb
+= stdata
.eq(pi
.st
.data
<< (lenexp
.addr_i
*8))
255 # TODO: replace with link to LoadStoreUnitInterface.x_store_data
256 # and also handle the ready/stall/busy protocol
257 stok
= self
.set_wr_data(m
, stdata
, lenexp
.lexp_o
)
258 sync
+= st_done
.s
.eq(1) # store done trigger
259 with m
.If(st_done
.q
):
260 comb
+= reset_l
.s
.eq(stok
) # reset mode after 1 cycle
262 # ugly hack, due to simultaneous addr req-go acknowledge
263 reset_delay
= Signal(reset_less
=True)
264 sync
+= reset_delay
.eq(reset_l
.q
)
265 with m
.If(reset_delay
):
266 comb
+= adrok_l
.r
.eq(1) # address reset
268 # after waiting one cycle (reset_l is "sync" mode), reset the port
269 with m
.If(reset_l
.q
):
270 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
271 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
272 comb
+= reset_l
.r
.eq(1) # clear reset
273 comb
+= adrok_l
.r
.eq(1) # address reset
274 comb
+= st_done
.r
.eq(1) # store done reset
276 # monitor for an exception or the completion of LD.
277 with m
.If(self
.pi
.addr_exc_o
):
278 comb
+= busy_l
.r
.eq(1)
280 # however ST needs one cycle before busy is reset
281 #with m.If(self.pi.st.ok | self.pi.ld.ok):
282 with m
.If(reset_l
.s
):
283 comb
+= cyc_l
.s
.eq(1)
286 comb
+= cyc_l
.r
.eq(1)
287 comb
+= busy_l
.r
.eq(1)
289 # busy latch outputs to interface
290 comb
+= pi
.busy_o
.eq(busy_l
.q
)
295 yield from self
.pi
.ports()
298 class TestMemoryPortInterface(PortInterfaceBase
):
299 """TestMemoryPortInterface
301 This is a test class for simple verification of the LDSTCompUnit
302 and for the simple core, to be able to run unit tests rapidly and
303 with less other code in the way.
305 Versions of this which are *compatible* (conform with PortInterface)
306 will include augmented-Wishbone Bus versions, including ones that
307 connect to L1, L2, MMU etc. etc. however this is the "base lowest
308 possible version that complies with PortInterface".
311 def __init__(self
, regwid
=64, addrwid
=4):
312 super().__init
__(regwid
, addrwid
)
313 # hard-code memory addressing width to 6 bits
314 self
.mem
= TestMemory(regwid
, 5, granularity
=regwid
//8, init
=False)
316 def set_wr_addr(self
, m
, addr
, mask
):
317 lsbaddr
, msbaddr
= self
.splitaddr(addr
)
318 m
.d
.comb
+= self
.mem
.wrport
.addr
.eq(msbaddr
)
320 def set_rd_addr(self
, m
, addr
, mask
):
321 lsbaddr
, msbaddr
= self
.splitaddr(addr
)
322 m
.d
.comb
+= self
.mem
.rdport
.addr
.eq(msbaddr
)
324 def set_wr_data(self
, m
, data
, wen
):
325 m
.d
.comb
+= self
.mem
.wrport
.data
.eq(data
) # write st to mem
326 m
.d
.comb
+= self
.mem
.wrport
.en
.eq(wen
) # enable writes
329 def get_rd_data(self
, m
):
330 return self
.mem
.rdport
.data
, Const(1, 1)
332 def elaborate(self
, platform
):
333 m
= super().elaborate(platform
)
335 # add TestMemory as submodule
336 m
.submodules
.mem
= self
.mem
341 yield from super().ports()