src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from openpower.decoder.power_enums import MSRSpec
  29 from soc.scoreboard.addr_match import LenExpand
  30 from soc.experiment.mem_types import LDSTException
  31
  32 # for testing purposes
  33 from soc.experiment.testmem import TestMemory
  34 #from soc.scoreboard.addr_split import LDSTSplitter
  35 from nmutil.util import Display
  36
  37 import unittest
  38
  39
  40 class PortInterface(RecordObject):
  41     """PortInterface
  42
  43     defines the interface - the API - that the LDSTCompUnit connects
  44     to.  note that this is NOT a "fire-and-forget" interface.  the
  45     LDSTCompUnit *must* be kept appraised that the request is in
  46     progress, and only when it has a 100% successful completion
  47     can the notification be given (busy dropped).
  48
  49     The interface FSM rules are as follows:
  50
  51     * if busy_o is asserted, a LD/ST is in progress.  further
  52       requests may not be made until busy_o is deasserted.
  53
  54     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  55       will immediately be asserted and remain asserted.
  56
  57     * addr.ok is to be asserted when the LD/ST address is known.
  58       addr.data is to be valid on the same cycle.
  59
  60       addr.ok and addr.data must REMAIN asserted until busy_o
  61       is de-asserted.  this ensures that there is no need
  62       for the L0 Cache/Buffer to have an additional address latch
  63       (because the LDSTCompUnit already has it)
  64
  65     * addr_ok_o (or exception.happened) must be waited for.  these will
  66       be asserted *only* for one cycle and one cycle only.
  67
  68     * exception.happened will be asserted if there is no chance that the
  69       memory request may be fulfilled.
  70
  71       busy_o is deasserted on the same cycle as exception.happened is asserted.
  72
  73     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  74       HUNDRED PERCENT guarantee that the memory request will be
  75       fulfilled.
  76
  77     * for a LD, ld.ok will be asserted - for only one clock cycle -
  78       at any point in the future that is acceptable to the underlying
  79       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  80
  81       busy_o is deasserted on the same cycle as ld.ok is asserted.
  82
  83     * for a ST, st.ok may be asserted only after addr_ok_o had been
  84       asserted, alongside valid st.data at the same time.  st.ok
  85       must only be asserted for one cycle.
  86
  87       the underlying Memory is REQUIRED to pick up that data and
  88       guarantee its delivery.  no back-acknowledgement is required.
  89
  90       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  91     """
  92
  93     def __init__(self, name=None, regwid=64, addrwid=64):
  94
  95         self._regwid = regwid
  96         self._addrwid = addrwid
  97
  98         RecordObject.__init__(self, name=name)
  99
 100         # distinguish op type (ld/st/dcbz/nc)
 101         self.is_ld_i    = Signal(reset_less=True)
 102         self.is_st_i    = Signal(reset_less=True)
 103         self.is_dcbz_i     = Signal(reset_less=True) # cache-line zeroing
 104         self.is_nc         = Signal()  # no cacheing
 105
 106         # LD/ST data length (TODO: other things may be needed)
 107         self.data_len = Signal(4, reset_less=True)
 108
 109         # atomic reservation (LR/SC - ldarx / stdcx etc.)
 110         self.reserve = Signal(reset_less=True)
 111
 112         # common signals
 113         self.busy_o = Signal(reset_less=True)     # do not use if busy
 114         self.go_die_i = Signal(reset_less=True)   # back to reset
 115         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 116         # addr is valid (TLB, L1 etc.)
 117         self.addr_ok_o = Signal(reset_less=True)
 118         self.exc_o = LDSTException("exc")
 119
 120         # LD/ST
 121         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 122         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 123         self.store_done = Data(1, "store_done_o") # store has been actioned
 124
 125         #only priv_mode = not msr_pr is used currently
 126         # TODO: connect signals
 127         self.virt_mode  = Signal() # ctrl.msr(MSR_DR);
 128         self.priv_mode  = Signal() # not ctrl.msr(MSR_PR);
 129         self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
 130
 131         # dcache
 132         self.ldst_error        = Signal()
 133         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 134         self.cache_paradox     = Signal()
 135
 136     def connect_port(self, inport):
 137         print("connect_port", self, inport)
 138         return [self.is_ld_i.eq(inport.is_ld_i),
 139                 self.is_st_i.eq(inport.is_st_i),
 140                 self.is_nc.eq(inport.is_nc),
 141                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 142                 self.data_len.eq(inport.data_len),
 143                 self.reserve.eq(inport.reserve),
 144                 self.go_die_i.eq(inport.go_die_i),
 145                 self.addr.data.eq(inport.addr.data),
 146                 self.addr.ok.eq(inport.addr.ok),
 147                 self.st.eq(inport.st),
 148                 self.virt_mode.eq(inport.virt_mode),
 149                 self.priv_mode.eq(inport.priv_mode),
 150                 self.mode_32bit.eq(inport.mode_32bit),
 151                 inport.ld.eq(self.ld),
 152                 inport.busy_o.eq(self.busy_o),
 153                 inport.addr_ok_o.eq(self.addr_ok_o),
 154                 inport.exc_o.eq(self.exc_o),
 155                 inport.store_done.eq(self.store_done),
 156                 inport.ldst_error.eq(self.ldst_error),
 157                 inport.cache_paradox.eq(self.cache_paradox)
 158                 ]
 159
 160
 161 class PortInterfaceBase(Elaboratable):
 162     """PortInterfaceBase
 163
 164     Base class for PortInterface-compliant Memory read/writers
 165     """
 166
 167     def __init__(self, regwid=64, addrwid=4):
 168         self.regwid = regwid
 169         self.addrwid = addrwid
 170         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 171
 172     @property
 173     def addrbits(self):
 174         return log2_int(self.regwid//8)
 175
 176     def splitaddr(self, addr):
 177         """split the address into top and bottom bits of the memory granularity
 178         """
 179         return addr[:self.addrbits], addr[self.addrbits:]
 180
 181     def connect_port(self, inport):
 182         return self.pi.connect_port(inport)
 183
 184     def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc): pass
 185     def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc): pass
 186     def set_wr_data(self, m, data, wen): pass
 187     def get_rd_data(self, m): pass
 188
 189     def elaborate(self, platform):
 190         m = Module()
 191         comb, sync = m.d.comb, m.d.sync
 192
 193         # state-machine latches
 194         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 195         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 196         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 197         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 198         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 199         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 200         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 201
 202         self.busy_l = busy_l
 203
 204         sync += st_done.s.eq(0)
 205         comb += st_done.r.eq(0)
 206         comb += st_active.r.eq(0)
 207         comb += ld_active.r.eq(0)
 208         comb += cyc_l.s.eq(0)
 209         comb += cyc_l.r.eq(0)
 210         comb += busy_l.s.eq(0)
 211         comb += busy_l.r.eq(0)
 212         sync += adrok_l.s.eq(0)
 213         comb += adrok_l.r.eq(0)
 214
 215         # expand ld/st binary length/addr[:3] into unary bitmap
 216         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 217
 218         lds = Signal(reset_less=True)
 219         sts = Signal(reset_less=True)
 220         pi = self.pi
 221         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 222         comb += sts.eq(pi.is_st_i)  # st-req signals
 223
 224         # TODO: construct an MSRspec here and pass it over in
 225         # self.set_rd_addr and set_wr_addr below rather than just pr
 226         pr = ~pi.priv_mode
 227         dr = pi.virt_mode
 228         sf = ~pi.mode_32bit
 229         msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 230
 231         # detect busy "edge"
 232         busy_delay = Signal()
 233         busy_edge = Signal()
 234         sync += busy_delay.eq(pi.busy_o)
 235         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 236
 237         # misalignment detection: bits at end of lenexpand are set.
 238         # when using the L0CacheBuffer "data expander" which splits requests
 239         # into *two* PortInterfaces, this acts as a "safety check".
 240         misalign = Signal()
 241         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 242
 243         # activate mode: only on "edge"
 244         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 245         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 246
 247         # LD/ST requested activates "busy" (only if not already busy)
 248         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 249             comb += busy_l.s.eq(~busy_delay)
 250             with m.If(self.pi.exc_o.happened):
 251                 sync += Display("fast exception")
 252
 253         # if now in "LD" mode: wait for addr_ok, then send the address out
 254         # to memory, acknowledge address, and send out LD data
 255         with m.If(ld_active.q):
 256             # set up LenExpander with the LD len and lower bits of addr
 257             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 258             comb += lenexp.len_i.eq(pi.data_len)
 259             comb += lenexp.addr_i.eq(lsbaddr)
 260             with m.If(pi.addr.ok & adrok_l.qn):
 261                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign,
 262                                     msr, pi.is_nc)
 263                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 264                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 265
 266         # if now in "ST" mode: likewise do the same but with "ST"
 267         # to memory, acknowledge address, and send out LD data
 268         with m.If(st_active.q):
 269             # set up LenExpander with the ST len and lower bits of addr
 270             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 271             comb += lenexp.len_i.eq(pi.data_len)
 272             comb += lenexp.addr_i.eq(lsbaddr)
 273             with m.If(pi.addr.ok):
 274                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, msr,
 275                                  pi.is_dcbz_i, pi.is_nc)
 276                 with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
 277                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 278                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 279
 280         # for LD mode, when addr has been "ok'd", assume that (because this
 281         # is a "Memory" test-class) the memory read data is valid.
 282         comb += reset_l.s.eq(0)
 283         comb += reset_l.r.eq(0)
 284         lddata = Signal(self.regwid, reset_less=True)
 285         data, ldok = self.get_rd_data(m)
 286         comb += lddata.eq((data & lenexp.rexp_o) >>
 287                           (lenexp.addr_i*8))
 288         with m.If(ld_active.q & adrok_l.q):
 289             # shift data down before pushing out.  requires masking
 290             # from the *byte*-expanded version of LenExpand output
 291             comb += pi.ld.data.eq(lddata)  # put data out
 292             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 293             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 294
 295         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 296         sync += st_done.s.eq(0)     # store done trigger
 297         with m.If(st_active.q & pi.st.ok):
 298             # shift data up before storing.  lenexp *bit* version of mask is
 299             # passed straight through as byte-level "write-enable" lines.
 300             stdata = Signal(self.regwid*2, reset_less=True)
 301             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 302             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 303             # and also handle the ready/stall/busy protocol
 304             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 305             sync += st_done.s.eq(~self.pi.exc_o.happened) # store done trigger
 306         with m.If(st_done.q):
 307             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 308
 309         # ugly hack, due to simultaneous addr req-go acknowledge
 310         reset_delay = Signal(reset_less=True)
 311         sync += reset_delay.eq(reset_l.q)
 312         with m.If(reset_delay):
 313             comb += adrok_l.r.eq(1)     # address reset
 314
 315         # after waiting one cycle (reset_l is "sync" mode), reset the port
 316         with m.If(reset_l.q):
 317             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 318             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 319             comb += reset_l.r.eq(1)     # clear reset
 320             comb += adrok_l.r.eq(1)     # address reset
 321             comb += st_done.r.eq(1)     # store done reset
 322
 323         # monitor for an exception, clear busy immediately
 324         with m.If(self.pi.exc_o.happened):
 325             comb += busy_l.r.eq(1)
 326             comb += reset_l.s.eq(1) # also reset whole unit
 327
 328         # however ST needs one cycle before busy is reset
 329         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 330         with m.If(reset_l.s):
 331             comb += cyc_l.s.eq(1)
 332
 333         with m.If(cyc_l.q):
 334             comb += cyc_l.r.eq(1)
 335             comb += busy_l.r.eq(1)
 336
 337         # busy latch outputs to interface
 338         if hasattr(self, "external_busy"):
 339             # when there is an extra (external) busy, include that here.
 340             # this is used e.g. in LoadStore1 when an instruction fault
 341             # is being processed (instr_fault) and stops Load/Store requests
 342             # from being made until it's done
 343             comb += pi.busy_o.eq(busy_l.q | self.external_busy(m))
 344         else:
 345             comb += pi.busy_o.eq(busy_l.q)
 346
 347         return m
 348
 349     def ports(self):
 350         yield from self.pi.ports()
 351
 352
 353 class TestMemoryPortInterface(PortInterfaceBase):
 354     """TestMemoryPortInterface
 355
 356     This is a test class for simple verification of the LDSTCompUnit
 357     and for the simple core, to be able to run unit tests rapidly and
 358     with less other code in the way.
 359
 360     Versions of this which are *compatible* (conform with PortInterface)
 361     will include augmented-Wishbone Bus versions, including ones that
 362     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 363     possible version that complies with PortInterface".
 364     """
 365
 366     def __init__(self, regwid=64, addrwid=4):
 367         super().__init__(regwid, addrwid)
 368         # hard-code memory addressing width to 6 bits
 369         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 370
 371     def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz, is_nc):
 372         lsbaddr, msbaddr = self.splitaddr(addr)
 373         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 374
 375     def set_rd_addr(self, m, addr, mask, misalign, msr, is_nc):
 376         lsbaddr, msbaddr = self.splitaddr(addr)
 377         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 378
 379     def set_wr_data(self, m, data, wen):
 380         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 381         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 382         return Const(1, 1)
 383
 384     def get_rd_data(self, m):
 385         return self.mem.rdport.data, Const(1, 1)
 386
 387     def elaborate(self, platform):
 388         m = super().elaborate(platform)
 389
 390         # add TestMemory as submodule
 391         m.submodules.mem = self.mem
 392
 393         return m
 394
 395     def ports(self):
 396         yield from super().ports()
 397         # TODO: memory ports