Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / experiment / pimem.py
2022-02-23 Luke Kenneth Casso... forgot to pass cix (cache-inhibited) through to LD...
2022-01-28 Luke Kenneth Casso... sort out misaligned store in LoadStore1
2022-01-16 Luke Kenneth Casso... pass over store_done correctly from dcache over PortInt...
2022-01-16 Luke Kenneth Casso... add CR0 to LDSTCompUnit, for reporting if LR/SC store...
2022-01-16 Luke Kenneth Casso... remove PortInterface mmu_done signal,
2022-01-15 Luke Kenneth Casso... add reserve (atomic) signal to LDST data structures...
2022-01-15 Luke Kenneth Casso... tidyup PortInterface
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error:
2021-12-13 Luke Kenneth Casso... fix up pr/dr/sf in PortInterfaceBase
2021-12-13 Luke Kenneth Casso... convert PortInterfaceBase to pass msr not msr_pr
2021-12-13 Luke Kenneth Casso... still have to import MSRSpec
2021-12-13 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-12-13 Luke Kenneth Casso... construct an MSRSpec in PortInterfaceBase (not used...
2021-12-13 Tobias Platenremove redundant MSRSpec from pimem
2021-12-13 Luke Kenneth Casso... whoops wrong variable names
2021-12-13 Luke Kenneth Casso... TODO comments about using MSRspec
2021-12-13 Luke Kenneth Casso... change PortInterface naming to msr not msr_pr in set_wr...
2021-12-13 Tobias Platenadd namedtuple proposed by lkcl in chat
2021-12-13 Tobias Platenadd signals to port interface as descibed in bug 756
2021-12-08 Luke Kenneth Casso... add new PortInterfaceBase external_busy() option
2021-12-04 Luke Kenneth Casso... remove DAR from PortInterface (where is the data going...
2021-12-03 Luke Kenneth Casso... fix PortInterfaceBase
2021-11-25 Tobias Platenpimem: reset on exception
2021-11-23 Tobias Platenpimem changes for st exception handling
2021-11-17 Tobias PlatenPortInterfaceBase: fix fast exception handling
2021-11-15 Tobias Platenreport dar on exception + test case
2021-11-11 Luke Kenneth Casso... TODO, implement is_dcbz
2021-10-08 Tobias Platenmore cleanup on pimem.py
2021-10-08 Tobias Platenan extra dcbz parameter in all six places
2021-10-08 Luke Kenneth Casso... have to remove dcbz from pimem.py entirely
2021-10-08 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-08 Tobias Platendcbz: cleanup
2021-10-08 Tobias Platendcbz symbol rename
2021-10-08 Tobias PlatenPortInterfaceBase: add dcbz handling
2021-10-03 Tobias Platenmore cleanup on pimem.py
2021-10-03 Tobias Platenan extra dcbz parameter in all six places
2021-10-02 Luke Kenneth Casso... have to remove dcbz from pimem.py entirely
2021-10-02 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-02 Tobias Platendcbz: cleanup
2021-10-02 Tobias Platendcbz symbol rename
2021-10-02 Tobias PlatenPortInterfaceBase: add dcbz handling
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox
2020-10-06 Tobias Platenremove redunant signals
2020-10-06 Luke Kenneth Casso... update comments on pimem.py
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-06 Luke Kenneth Casso... move LDSTException to mem_types
2020-10-06 Luke Kenneth Casso... add LDSTException to PortInterface
2020-09-15 Luke Kenneth Casso... add extra "modes" to PortInterface
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-20 Tobias Platentestcase refactoring
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface
2020-08-19 Luke Kenneth Casso... more subtle interactions between wishbone bus when...
2020-08-16 Luke Kenneth Casso... fix LD/ST pimem issue with rising_edge detection
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Luke Kenneth Casso... fix LDST PortInterface FSM interaction
2020-08-03 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=446
2020-08-03 Tobias PlatenLDSTSplitter: report exception
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...