src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import verilog, rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23 from nmigen.hdl.rec import Record, Layout
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.decoder.power_enums import InternalOp
  28 from soc.regfile.regfile import ortreereduce
  29 from nmutil.util import treereduce
  30
  31 from soc.decoder.power_decoder2 import Data
  32 #from nmutil.picker import PriorityPicker
  33 from nmigen.lib.coding import PriorityEncoder
  34 from soc.scoreboard.addr_split import LDSTSplitter
  35 from soc.scoreboard.addr_match import LenExpand
  36
  37 # for testing purposes
  38 from soc.experiment.testmem import TestMemory # TODO: replace with TMLSUI
  39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
  40
  41 import unittest
  42
  43
  44 class PortInterface(RecordObject):
  45     """PortInterface
  46
  47     defines the interface - the API - that the LDSTCompUnit connects
  48     to.  note that this is NOT a "fire-and-forget" interface.  the
  49     LDSTCompUnit *must* be kept appraised that the request is in
  50     progress, and only when it has a 100% successful completion
  51     can the notification be given (busy dropped).
  52
  53     The interface FSM rules are as follows:
  54
  55     * if busy_o is asserted, a LD/ST is in progress.  further
  56       requests may not be made until busy_o is deasserted.
  57
  58     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  59       will immediately be asserted and remain asserted.
  60
  61     * addr.ok is to be asserted when the LD/ST address is known.
  62       addr.data is to be valid on the same cycle.
  63
  64       addr.ok and addr.data must REMAIN asserted until busy_o
  65       is de-asserted.  this ensures that there is no need
  66       for the L0 Cache/Buffer to have an additional address latch
  67       (because the LDSTCompUnit already has it)
  68
  69     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  70       be asserted *only* for one cycle and one cycle only.
  71
  72     * addr_exc_o will be asserted if there is no chance that the
  73       memory request may be fulfilled.
  74
  75       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  76
  77     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  78       HUNDRED PERCENT guarantee that the memory request will be
  79       fulfilled.
  80
  81     * for a LD, ld.ok will be asserted - for only one clock cycle -
  82       at any point in the future that is acceptable to the underlying
  83       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  84
  85       busy_o is deasserted on the same cycle as ld.ok is asserted.
  86
  87     * for a ST, st.ok may be asserted only after addr_ok_o had been
  88       asserted, alongside valid st.data at the same time.  st.ok
  89       must only be asserted for one cycle.
  90
  91       the underlying Memory is REQUIRED to pick up that data and
  92       guarantee its delivery.  no back-acknowledgement is required.
  93
  94       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  95     """
  96
  97     def __init__(self, name=None, regwid=64, addrwid=48):
  98
  99         self._regwid = regwid
 100         self._addrwid = addrwid
 101
 102         RecordObject.__init__(self, name=name)
 103
 104         # distinguish op type (ld/st)
 105         self.is_ld_i = Signal(reset_less=True)
 106         self.is_st_i = Signal(reset_less=True)
 107
 108         # LD/ST data length (TODO: other things may be needed)
 109         self.data_len = Signal(4, reset_less=True)
 110
 111         # common signals
 112         self.busy_o = Signal(reset_less=True)     # do not use if busy
 113         self.go_die_i = Signal(reset_less=True)   # back to reset
 114         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 115         # addr is valid (TLB, L1 etc.)
 116         self.addr_ok_o = Signal(reset_less=True)
 117         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 118
 119         # LD/ST
 120         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 121         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 122
 123
 124 class LDSTPort(Elaboratable):
 125     def __init__(self, idx, regwid=64, addrwid=48):
 126         self.pi = PortInterface("ldst_port%d" % idx, regwid, addrwid)
 127
 128     def elaborate(self, platform):
 129         m = Module()
 130         comb, sync = m.d.comb, m.d.sync
 131
 132         # latches
 133         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 134         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 135         comb += cyc_l.s.eq(0)
 136         comb += cyc_l.r.eq(0)
 137
 138         # this is a little weird: we let the L0Cache/Buffer set
 139         # the outputs: this module just monitors "state".
 140
 141         # LD/ST requested activates "busy"
 142         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 143             comb += busy_l.s.eq(1)
 144
 145         # monitor for an exception or the completion of LD.
 146         with m.If(self.pi.addr_exc_o):
 147             comb += busy_l.r.eq(1)
 148
 149         # however ST needs one cycle before busy is reset
 150         with m.If(self.pi.st.ok | self.pi.ld.ok):
 151             comb += cyc_l.s.eq(1)
 152
 153         with m.If(cyc_l.q):
 154             comb += cyc_l.r.eq(1)
 155             comb += busy_l.r.eq(1)
 156
 157         # busy latch outputs to interface
 158         comb += self.pi.busy_o.eq(busy_l.q)
 159
 160         return m
 161
 162     def connect_port(self, inport):
 163         print ("connect_port", self.pi, inport)
 164         return [self.pi.is_ld_i.eq(inport.is_ld_i),
 165                 self.pi.is_st_i.eq(inport.is_st_i),
 166                 self.pi.data_len.eq(inport.data_len),
 167                 self.pi.go_die_i.eq(inport.go_die_i),
 168                 self.pi.addr.eq(inport.addr),
 169                 self.pi.st.eq(inport.st),
 170                 inport.ld.eq(self.pi.ld),
 171                 inport.busy_o.eq(self.pi.busy_o),
 172                 inport.addr_ok_o.eq(self.pi.addr_ok_o),
 173                 inport.addr_exc_o.eq(self.pi.addr_exc_o),
 174                 ]
 175
 176     def __iter__(self):
 177         yield self.pi.is_ld_i
 178         yield self.pi.is_st_i
 179         yield from self.pi.data_len
 180         yield self.pi.busy_o
 181         yield self.pi.go_die_i
 182         yield from self.pi.addr.ports()
 183         yield self.pi.addr_ok_o
 184         yield self.pi.addr_exc_o
 185
 186         yield from self.pi.ld.ports()
 187         yield from self.pi.st.ports()
 188
 189     def ports(self):
 190         return list(self)
 191
 192
 193 class TestMemoryPortInterface(Elaboratable):
 194     """TestMemoryPortInterface
 195
 196     This is a test class for simple verification of the LDSTCompUnit
 197     and for the simple core, to be able to run unit tests rapidly and
 198     with less other code in the way.
 199
 200     Versions of this which are *compatible* (conform with PortInterface)
 201     will include augmented-Wishbone Bus versions, including ones that
 202     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 203     possible version that complies with PortInterface".
 204     """
 205
 206     def __init__(self, regwid=64, addrwid=4):
 207         self.mem = TestMemory(regwid, addrwid, granularity=regwid//8)
 208         self.regwid = regwid
 209         self.addrwid = addrwid
 210         self.pi = LDSTPort(0, regwid, addrwid)
 211
 212     @property
 213     def addrbits(self):
 214         return log2_int(self.mem.regwid//8)
 215
 216     def splitaddr(self, addr):
 217         """split the address into top and bottom bits of the memory granularity
 218         """
 219         return addr[:self.addrbits], addr[self.addrbits:]
 220
 221     def connect_port(self, inport):
 222         return self.pi.connect_port(inport)
 223
 224     def elaborate(self, platform):
 225         m = Module()
 226         comb, sync = m.d.comb, m.d.sync
 227
 228         # add TestMemory as submodule
 229         m.submodules.mem = self.mem
 230
 231         # connect the ports as modules
 232         m.submodules.port0 = self.pi
 233
 234         # state-machine latches
 235         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 236         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 237         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 238         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 239
 240         # expand ld/st binary length/addr[:3] into unary bitmap
 241         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 242
 243         lds = Signal(reset_less=True)
 244         sts = Signal(reset_less=True)
 245         pi = self.pi.pi
 246         comb += lds.eq(pi.is_ld_i & pi.busy_o)  # ld-req signals
 247         comb += sts.eq(pi.is_st_i & pi.busy_o)  # st-req signals
 248
 249         # convenience variables to reference the "picked" port
 250         ldport = pi
 251         stport = pi
 252         # and the memory ports
 253         rdport = self.mem.rdport
 254         wrport = self.mem.wrport
 255
 256         # Priority-Pickers pick one and only one request, capture its index.
 257         # from that point on this code *only* "listens" to that port.
 258
 259         sync += adrok_l.s.eq(0)
 260         comb += adrok_l.r.eq(0)
 261         with m.If(lds):
 262             comb += ld_active.s.eq(1)  # activate LD mode
 263         with m.Elif(sts):
 264             comb += st_active.s.eq(1)  # activate ST mode
 265
 266         # from this point onwards, with the port "picked", it stays picked
 267         # until ld_active (or st_active) are de-asserted.
 268
 269         # if now in "LD" mode: wait for addr_ok, then send the address out
 270         # to memory, acknowledge address, and send out LD data
 271         with m.If(ld_active.q):
 272             # set up LenExpander with the LD len and lower bits of addr
 273             lsbaddr, msbaddr = self.splitaddr(ldport.addr.data)
 274             comb += lenexp.len_i.eq(ldport.data_len)
 275             comb += lenexp.addr_i.eq(lsbaddr)
 276             with m.If(ldport.addr.ok & adrok_l.qn):
 277                 comb += rdport.addr.eq(msbaddr) # addr ok, send thru
 278                 comb += ldport.addr_ok_o.eq(1)  # acknowledge addr ok
 279                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 280
 281         # if now in "ST" mode: likewise do the same but with "ST"
 282         # to memory, acknowledge address, and send out LD data
 283         with m.If(st_active.q):
 284             # set up LenExpander with the ST len and lower bits of addr
 285             lsbaddr, msbaddr = self.splitaddr(stport.addr.data)
 286             comb += lenexp.len_i.eq(stport.data_len)
 287             comb += lenexp.addr_i.eq(lsbaddr)
 288             with m.If(stport.addr.ok):
 289                 comb += wrport.addr.eq(msbaddr)  # addr ok, send thru
 290                 with m.If(adrok_l.qn):
 291                     comb += stport.addr_ok_o.eq(1)  # acknowledge addr ok
 292                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 293
 294         # NOTE: in both these, below, the port itself takes care
 295         # of de-asserting its "busy_o" signal, based on either ld.ok going
 296         # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
 297
 298         # for LD mode, when addr has been "ok'd", assume that (because this
 299         # is a "Memory" test-class) the memory read data is valid.
 300         comb += reset_l.s.eq(0)
 301         comb += reset_l.r.eq(0)
 302         with m.If(ld_active.q & adrok_l.q):
 303             # shift data down before pushing out.  requires masking
 304             # from the *byte*-expanded version of LenExpand output
 305             lddata = Signal(self.regwid, reset_less=True)
 306             # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
 307             # and also handle the ready/stall/busy protocol
 308             comb += lddata.eq((rdport.data & lenexp.rexp_o) >>
 309                               (lenexp.addr_i*8))
 310             comb += ldport.ld.data.eq(lddata)  # put data out
 311             comb += ldport.ld.ok.eq(1)           # indicate data valid
 312             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 313
 314         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 315         with m.If(st_active.q & stport.st.ok):
 316             # shift data up before storing.  lenexp *bit* version of mask is
 317             # passed straight through as byte-level "write-enable" lines.
 318             stdata = Signal(self.regwid, reset_less=True)
 319             comb += stdata.eq(stport.st.data << (lenexp.addr_i*8))
 320             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 321             # and also handle the ready/stall/busy protocol
 322             comb += wrport.data.eq(stdata)  # write st to mem
 323             comb += wrport.en.eq(lenexp.lexp_o) # enable writes
 324             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 325
 326         # ugly hack, due to simultaneous addr req-go acknowledge
 327         reset_delay = Signal(reset_less=True)
 328         sync += reset_delay.eq(reset_l.q)
 329         with m.If(reset_delay):
 330             comb += adrok_l.r.eq(1)     # address reset
 331
 332         # after waiting one cycle (reset_l is "sync" mode), reset the port
 333         with m.If(reset_l.q):
 334             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 335             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 336             comb += reset_l.r.eq(1)     # clear reset
 337             comb += adrok_l.r.eq(1)     # address reset
 338
 339         return m
 340
 341     def ports(self):
 342         for p in self.dports:
 343             yield from p.ports()
 344
 345
 346 def wait_busy(port, no=False):
 347     while True:
 348         busy = yield port.pi.busy_o
 349         print("busy", no, busy)
 350         if bool(busy) == no:
 351             break
 352         yield
 353
 354
 355 def wait_addr(port):
 356     while True:
 357         addr_ok = yield port.pi.addr_ok_o
 358         print("addrok", addr_ok)
 359         if not addr_ok:
 360             break
 361         yield
 362
 363
 364 def wait_ldok(port):
 365     while True:
 366         ldok = yield port.pi.ld.ok
 367         print("ldok", ldok)
 368         if ldok:
 369             break
 370         yield
 371
 372
 373 def l0_cache_st(dut, addr, data, datalen):
 374     mem = dut.mem
 375     port1 = dut.pi
 376
 377     # have to wait until not busy
 378     yield from wait_busy(port1, no=False)    # wait until not busy
 379
 380     # set up a ST on the port.  address first:
 381     yield port1.pi.is_st_i.eq(1)  # indicate ST
 382     yield port1.pi.data_len.eq(datalen)  # ST length (1/2/4/8)
 383
 384     yield port1.pi.addr.data.eq(addr)  # set address
 385     yield port1.pi.addr.ok.eq(1)  # set ok
 386     yield from wait_addr(port1)             # wait until addr ok
 387     # yield # not needed, just for checking
 388     # yield # not needed, just for checking
 389     # assert "ST" for one cycle (required by the API)
 390     yield port1.pi.st.data.eq(data)
 391     yield port1.pi.st.ok.eq(1)
 392     yield
 393     yield port1.pi.st.ok.eq(0)
 394
 395     # can go straight to reset.
 396     yield port1.pi.is_st_i.eq(0)  # end
 397     yield port1.pi.addr.ok.eq(0)  # set !ok
 398     # yield from wait_busy(port1, False)    # wait until not busy
 399
 400
 401 def l0_cache_ld(dut, addr, datalen, expected):
 402
 403     mem = dut.mem
 404     port1 = dut.pi
 405
 406     # have to wait until not busy
 407     yield from wait_busy(port1, no=False)    # wait until not busy
 408
 409     # set up a LD on the port.  address first:
 410     yield port1.pi.is_ld_i.eq(1)  # indicate LD
 411     yield port1.pi.data_len.eq(datalen)  # LD length (1/2/4/8)
 412
 413     yield port1.pi.addr.data.eq(addr)  # set address
 414     yield port1.pi.addr.ok.eq(1)  # set ok
 415     yield from wait_addr(port1)             # wait until addr ok
 416
 417     yield from wait_ldok(port1)             # wait until ld ok
 418     data = yield port1.pi.ld.data
 419
 420     # cleanup
 421     yield port1.pi.is_ld_i.eq(0)  # end
 422     yield port1.pi.addr.ok.eq(0)  # set !ok
 423     # yield from wait_busy(port1, no=False)    # wait until not busy
 424
 425     return data
 426
 427
 428 def l0_cache_ldst(arg, dut):
 429     yield
 430     addr = 0x2
 431     data = 0xbeef
 432     data2 = 0xf00f
 433     #data = 0x4
 434     yield from l0_cache_st(dut, 0x2, data, 2)
 435     yield from l0_cache_st(dut, 0x4, data2, 2)
 436     result = yield from l0_cache_ld(dut, 0x2, 2, data)
 437     result2 = yield from l0_cache_ld(dut, 0x4, 2, data2)
 438     yield
 439     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 440     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 441
 442
 443
 444 class TestPIMem(unittest.TestCase):
 445
 446     def test_pi_mem(self):
 447
 448         dut = TestMemoryPortInterface(regwid=64)
 449         #vl = rtlil.convert(dut, ports=dut.ports())
 450         #with open("test_basic_l0_cache.il", "w") as f:
 451         #    f.write(vl)
 452
 453         run_simulation(dut, l0_cache_ldst(self, dut),
 454                        vcd_name='test_pi_mem_basic.vcd')
 455
 456
 457 if __name__ == '__main__':
 458     unittest.main(exit=False)
 459