3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
, Settle
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
23 from nmigen
.hdl
.rec
import Record
, Layout
25 from nmutil
.latch
import SRLatch
, latchregister
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.decoder
.power_enums
import InternalOp
28 from soc
.regfile
.regfile
import ortreereduce
29 from nmutil
.util
import treereduce
31 from soc
.decoder
.power_decoder2
import Data
32 #from nmutil.picker import PriorityPicker
33 from nmigen
.lib
.coding
import PriorityEncoder
34 from soc
.scoreboard
.addr_split
import LDSTSplitter
35 from soc
.scoreboard
.addr_match
import LenExpand
37 # for testing purposes
38 from soc
.experiment
.testmem
import TestMemory
# TODO: replace with TMLSUI
39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
44 class PortInterface(RecordObject
):
47 defines the interface - the API - that the LDSTCompUnit connects
48 to. note that this is NOT a "fire-and-forget" interface. the
49 LDSTCompUnit *must* be kept appraised that the request is in
50 progress, and only when it has a 100% successful completion
51 can the notification be given (busy dropped).
53 The interface FSM rules are as follows:
55 * if busy_o is asserted, a LD/ST is in progress. further
56 requests may not be made until busy_o is deasserted.
58 * only one of is_ld_i or is_st_i may be asserted. busy_o
59 will immediately be asserted and remain asserted.
61 * addr.ok is to be asserted when the LD/ST address is known.
62 addr.data is to be valid on the same cycle.
64 addr.ok and addr.data must REMAIN asserted until busy_o
65 is de-asserted. this ensures that there is no need
66 for the L0 Cache/Buffer to have an additional address latch
67 (because the LDSTCompUnit already has it)
69 * addr_ok_o (or addr_exc_o) must be waited for. these will
70 be asserted *only* for one cycle and one cycle only.
72 * addr_exc_o will be asserted if there is no chance that the
73 memory request may be fulfilled.
75 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
77 * conversely: addr_ok_o must *ONLY* be asserted if there is a
78 HUNDRED PERCENT guarantee that the memory request will be
81 * for a LD, ld.ok will be asserted - for only one clock cycle -
82 at any point in the future that is acceptable to the underlying
83 Memory subsystem. the recipient MUST latch ld.data on that cycle.
85 busy_o is deasserted on the same cycle as ld.ok is asserted.
87 * for a ST, st.ok may be asserted only after addr_ok_o had been
88 asserted, alongside valid st.data at the same time. st.ok
89 must only be asserted for one cycle.
91 the underlying Memory is REQUIRED to pick up that data and
92 guarantee its delivery. no back-acknowledgement is required.
94 busy_o is deasserted on the cycle AFTER st.ok is asserted.
97 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
100 self
._addrwid
= addrwid
102 RecordObject
.__init
__(self
, name
=name
)
104 # distinguish op type (ld/st)
105 self
.is_ld_i
= Signal(reset_less
=True)
106 self
.is_st_i
= Signal(reset_less
=True)
108 # LD/ST data length (TODO: other things may be needed)
109 self
.data_len
= Signal(4, reset_less
=True)
112 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
113 self
.go_die_i
= Signal(reset_less
=True) # back to reset
114 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
115 # addr is valid (TLB, L1 etc.)
116 self
.addr_ok_o
= Signal(reset_less
=True)
117 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
120 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
121 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
124 class LDSTPort(Elaboratable
):
125 def __init__(self
, idx
, regwid
=64, addrwid
=48):
126 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
128 def elaborate(self
, platform
):
130 comb
, sync
= m
.d
.comb
, m
.d
.sync
133 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
134 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
135 comb
+= cyc_l
.s
.eq(0)
136 comb
+= cyc_l
.r
.eq(0)
138 # this is a little weird: we let the L0Cache/Buffer set
139 # the outputs: this module just monitors "state".
141 # LD/ST requested activates "busy"
142 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
143 comb
+= busy_l
.s
.eq(1)
145 # monitor for an exception or the completion of LD.
146 with m
.If(self
.pi
.addr_exc_o
):
147 comb
+= busy_l
.r
.eq(1)
149 # however ST needs one cycle before busy is reset
150 with m
.If(self
.pi
.st
.ok | self
.pi
.ld
.ok
):
151 comb
+= cyc_l
.s
.eq(1)
154 comb
+= cyc_l
.r
.eq(1)
155 comb
+= busy_l
.r
.eq(1)
157 # busy latch outputs to interface
158 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
163 yield self
.pi
.is_ld_i
164 yield self
.pi
.is_st_i
165 yield from self
.pi
.op
.ports()
167 yield self
.pi
.go_die_i
168 yield from self
.pi
.addr
.ports()
169 yield self
.pi
.addr_ok_o
170 yield self
.pi
.addr_exc_o
172 yield from self
.pi
.ld
.ports()
173 yield from self
.pi
.st
.ports()
179 class TestMemoryPortInterface(Elaboratable
):
180 """TestMemoryPortInterface
182 This is a test class for simple verification of the LDSTCompUnit
183 and for the simple core, to be able to run unit tests rapidly and
184 with less other code in the way.
186 Versions of this which are *compatible* (conform with PortInterface)
187 will include augmented-Wishbone Bus versions, including ones that
188 connect to L1, L2, MMU etc. etc. however this is the "base lowest
189 possible version that complies with PortInterface".
192 def __init__(self
, regwid
=64, addrwid
=4):
193 self
.mem
= TestMemory(regwid
, addrwid
, granularity
=regwid
//8)
195 self
.addrwid
= addrwid
196 self
.pi
= LDSTPort(0, regwid
, addrwid
)
200 return log2_int(self
.mem
.regwid
//8)
202 def splitaddr(self
, addr
):
203 """split the address into top and bottom bits of the memory granularity
205 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
207 def elaborate(self
, platform
):
209 comb
, sync
= m
.d
.comb
, m
.d
.sync
211 # add TestMemory as submodule
212 m
.submodules
.mem
= self
.mem
214 # connect the ports as modules
215 m
.submodules
.port0
= self
.pi
217 # state-machine latches
218 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
219 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
220 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
221 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
223 # expand ld/st binary length/addr[:3] into unary bitmap
224 m
.submodules
.lenexp
= lenexp
= LenExpand(4, 8)
226 lds
= Signal(reset_less
=True)
227 sts
= Signal(reset_less
=True)
229 comb
+= lds
.eq(pi
.is_ld_i
& pi
.busy_o
) # ld-req signals
230 comb
+= sts
.eq(pi
.is_st_i
& pi
.busy_o
) # st-req signals
232 # convenience variables to reference the "picked" port
235 # and the memory ports
236 rdport
= self
.mem
.rdport
237 wrport
= self
.mem
.wrport
239 # Priority-Pickers pick one and only one request, capture its index.
240 # from that point on this code *only* "listens" to that port.
242 sync
+= adrok_l
.s
.eq(0)
243 comb
+= adrok_l
.r
.eq(0)
245 comb
+= ld_active
.s
.eq(1) # activate LD mode
247 comb
+= st_active
.s
.eq(1) # activate ST mode
249 # from this point onwards, with the port "picked", it stays picked
250 # until ld_active (or st_active) are de-asserted.
252 # if now in "LD" mode: wait for addr_ok, then send the address out
253 # to memory, acknowledge address, and send out LD data
254 with m
.If(ld_active
.q
):
255 # set up LenExpander with the LD len and lower bits of addr
256 lsbaddr
, msbaddr
= self
.splitaddr(ldport
.addr
.data
)
257 comb
+= lenexp
.len_i
.eq(ldport
.data_len
)
258 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
259 with m
.If(ldport
.addr
.ok
& adrok_l
.qn
):
260 comb
+= rdport
.addr
.eq(msbaddr
) # addr ok, send thru
261 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
262 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
264 # if now in "ST" mode: likewise do the same but with "ST"
265 # to memory, acknowledge address, and send out LD data
266 with m
.If(st_active
.q
):
267 # set up LenExpander with the ST len and lower bits of addr
268 lsbaddr
, msbaddr
= self
.splitaddr(stport
.addr
.data
)
269 comb
+= lenexp
.len_i
.eq(stport
.data_len
)
270 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
271 with m
.If(stport
.addr
.ok
):
272 comb
+= wrport
.addr
.eq(msbaddr
) # addr ok, send thru
273 with m
.If(adrok_l
.qn
):
274 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
275 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
277 # NOTE: in both these, below, the port itself takes care
278 # of de-asserting its "busy_o" signal, based on either ld.ok going
279 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
281 # for LD mode, when addr has been "ok'd", assume that (because this
282 # is a "Memory" test-class) the memory read data is valid.
283 comb
+= reset_l
.s
.eq(0)
284 comb
+= reset_l
.r
.eq(0)
285 with m
.If(ld_active
.q
& adrok_l
.q
):
286 # shift data down before pushing out. requires masking
287 # from the *byte*-expanded version of LenExpand output
288 lddata
= Signal(self
.regwid
, reset_less
=True)
289 # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
290 # and also handle the ready/stall/busy protocol
291 comb
+= lddata
.eq((rdport
.data
& lenexp
.rexp_o
) >>
293 comb
+= ldport
.ld
.data
.eq(lddata
) # put data out
294 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
295 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
297 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
298 with m
.If(st_active
.q
& stport
.st
.ok
):
299 # shift data up before storing. lenexp *bit* version of mask is
300 # passed straight through as byte-level "write-enable" lines.
301 stdata
= Signal(self
.regwid
, reset_less
=True)
302 comb
+= stdata
.eq(stport
.st
.data
<< (lenexp
.addr_i
*8))
303 # TODO: replace with link to LoadStoreUnitInterface.x_store_data
304 # and also handle the ready/stall/busy protocol
305 comb
+= wrport
.data
.eq(stdata
) # write st to mem
306 comb
+= wrport
.en
.eq(lenexp
.lexp_o
) # enable writes
307 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
309 # ugly hack, due to simultaneous addr req-go acknowledge
310 reset_delay
= Signal(reset_less
=True)
311 sync
+= reset_delay
.eq(reset_l
.q
)
312 with m
.If(reset_delay
):
313 comb
+= adrok_l
.r
.eq(1) # address reset
315 # after waiting one cycle (reset_l is "sync" mode), reset the port
316 with m
.If(reset_l
.q
):
317 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
318 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
319 comb
+= reset_l
.r
.eq(1) # clear reset
320 comb
+= adrok_l
.r
.eq(1) # address reset
325 for p
in self
.dports
:
329 def wait_busy(port
, no
=False):
331 busy
= yield port
.pi
.busy_o
332 print("busy", no
, busy
)
340 addr_ok
= yield port
.pi
.addr_ok_o
341 print("addrok", addr_ok
)
349 ldok
= yield port
.pi
.ld
.ok
356 def l0_cache_st(dut
, addr
, data
, datalen
):
360 # have to wait until not busy
361 yield from wait_busy(port1
, no
=False) # wait until not busy
363 # set up a ST on the port. address first:
364 yield port1
.pi
.is_st_i
.eq(1) # indicate ST
365 yield port1
.pi
.data_len
.eq(datalen
) # ST length (1/2/4/8)
367 yield port1
.pi
.addr
.data
.eq(addr
) # set address
368 yield port1
.pi
.addr
.ok
.eq(1) # set ok
369 yield from wait_addr(port1
) # wait until addr ok
370 # yield # not needed, just for checking
371 # yield # not needed, just for checking
372 # assert "ST" for one cycle (required by the API)
373 yield port1
.pi
.st
.data
.eq(data
)
374 yield port1
.pi
.st
.ok
.eq(1)
376 yield port1
.pi
.st
.ok
.eq(0)
378 # can go straight to reset.
379 yield port1
.pi
.is_st_i
.eq(0) # end
380 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
381 # yield from wait_busy(port1, False) # wait until not busy
384 def l0_cache_ld(dut
, addr
, datalen
, expected
):
389 # have to wait until not busy
390 yield from wait_busy(port1
, no
=False) # wait until not busy
392 # set up a LD on the port. address first:
393 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
394 yield port1
.pi
.data_len
.eq(datalen
) # LD length (1/2/4/8)
396 yield port1
.pi
.addr
.data
.eq(addr
) # set address
397 yield port1
.pi
.addr
.ok
.eq(1) # set ok
398 yield from wait_addr(port1
) # wait until addr ok
400 yield from wait_ldok(port1
) # wait until ld ok
401 data
= yield port1
.pi
.ld
.data
404 yield port1
.pi
.is_ld_i
.eq(0) # end
405 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
406 # yield from wait_busy(port1, no=False) # wait until not busy
411 def l0_cache_ldst(arg
, dut
):
417 yield from l0_cache_st(dut
, 0x2, data
, 2)
418 yield from l0_cache_st(dut
, 0x4, data2
, 2)
419 result
= yield from l0_cache_ld(dut
, 0x2, 2, data
)
420 result2
= yield from l0_cache_ld(dut
, 0x4, 2, data2
)
422 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
423 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
427 class TestPIMem(unittest
.TestCase
):
429 def test_pi_mem(self
):
431 dut
= TestMemoryPortInterface(regwid
=64)
432 #vl = rtlil.convert(dut, ports=dut.ports())
433 #with open("test_basic_l0_cache.il", "w") as f:
436 run_simulation(dut
, l0_cache_ldst(self
, dut
),
437 vcd_name
='test_pi_mem_basic.vcd')
440 if __name__
== '__main__':
441 unittest
.main(exit
=False)