3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
, Settle
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
23 from nmigen
.hdl
.rec
import Record
, Layout
25 from nmutil
.latch
import SRLatch
, latchregister
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.decoder
.power_enums
import InternalOp
28 from soc
.regfile
.regfile
import ortreereduce
29 from nmutil
.util
import treereduce
31 from soc
.decoder
.power_decoder2
import Data
32 #from nmutil.picker import PriorityPicker
33 from nmigen
.lib
.coding
import PriorityEncoder
34 from soc
.scoreboard
.addr_split
import LDSTSplitter
35 from soc
.scoreboard
.addr_match
import LenExpand
37 # for testing purposes
38 from soc
.experiment
.testmem
import TestMemory
# TODO: replace with TMLSUI
39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
44 class PortInterface(RecordObject
):
47 defines the interface - the API - that the LDSTCompUnit connects
48 to. note that this is NOT a "fire-and-forget" interface. the
49 LDSTCompUnit *must* be kept appraised that the request is in
50 progress, and only when it has a 100% successful completion
51 can the notification be given (busy dropped).
53 The interface FSM rules are as follows:
55 * if busy_o is asserted, a LD/ST is in progress. further
56 requests may not be made until busy_o is deasserted.
58 * only one of is_ld_i or is_st_i may be asserted. busy_o
59 will immediately be asserted and remain asserted.
61 * addr.ok is to be asserted when the LD/ST address is known.
62 addr.data is to be valid on the same cycle.
64 addr.ok and addr.data must REMAIN asserted until busy_o
65 is de-asserted. this ensures that there is no need
66 for the L0 Cache/Buffer to have an additional address latch
67 (because the LDSTCompUnit already has it)
69 * addr_ok_o (or addr_exc_o) must be waited for. these will
70 be asserted *only* for one cycle and one cycle only.
72 * addr_exc_o will be asserted if there is no chance that the
73 memory request may be fulfilled.
75 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
77 * conversely: addr_ok_o must *ONLY* be asserted if there is a
78 HUNDRED PERCENT guarantee that the memory request will be
81 * for a LD, ld.ok will be asserted - for only one clock cycle -
82 at any point in the future that is acceptable to the underlying
83 Memory subsystem. the recipient MUST latch ld.data on that cycle.
85 busy_o is deasserted on the same cycle as ld.ok is asserted.
87 * for a ST, st.ok may be asserted only after addr_ok_o had been
88 asserted, alongside valid st.data at the same time. st.ok
89 must only be asserted for one cycle.
91 the underlying Memory is REQUIRED to pick up that data and
92 guarantee its delivery. no back-acknowledgement is required.
94 busy_o is deasserted on the cycle AFTER st.ok is asserted.
97 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
100 self
._addrwid
= addrwid
102 RecordObject
.__init
__(self
, name
=name
)
104 # distinguish op type (ld/st)
105 self
.is_ld_i
= Signal(reset_less
=True)
106 self
.is_st_i
= Signal(reset_less
=True)
108 # LD/ST data length (TODO: other things may be needed)
109 self
.data_len
= Signal(4, reset_less
=True)
112 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
113 self
.go_die_i
= Signal(reset_less
=True) # back to reset
114 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
115 # addr is valid (TLB, L1 etc.)
116 self
.addr_ok_o
= Signal(reset_less
=True)
117 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
120 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
121 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
124 class LDSTPort(Elaboratable
):
125 def __init__(self
, idx
, regwid
=64, addrwid
=48):
126 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
128 def elaborate(self
, platform
):
130 comb
, sync
= m
.d
.comb
, m
.d
.sync
133 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
134 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
135 comb
+= cyc_l
.s
.eq(0)
136 comb
+= cyc_l
.r
.eq(0)
138 # this is a little weird: we let the L0Cache/Buffer set
139 # the outputs: this module just monitors "state".
141 # LD/ST requested activates "busy"
142 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
143 comb
+= busy_l
.s
.eq(1)
145 # monitor for an exception or the completion of LD.
146 with m
.If(self
.pi
.addr_exc_o
):
147 comb
+= busy_l
.r
.eq(1)
149 # however ST needs one cycle before busy is reset
150 with m
.If(self
.pi
.st
.ok | self
.pi
.ld
.ok
):
151 comb
+= cyc_l
.s
.eq(1)
154 comb
+= cyc_l
.r
.eq(1)
155 comb
+= busy_l
.r
.eq(1)
157 # busy latch outputs to interface
158 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
162 def connect_port(self
, inport
):
163 print ("connect_port", self
.pi
, inport
)
164 return [self
.pi
.is_ld_i
.eq(inport
.is_ld_i
),
165 self
.pi
.is_st_i
.eq(inport
.is_st_i
),
166 self
.pi
.data_len
.eq(inport
.data_len
),
167 self
.pi
.go_die_i
.eq(inport
.go_die_i
),
168 self
.pi
.addr
.data
.eq(inport
.addr
.data
),
169 self
.pi
.addr
.ok
.eq(inport
.addr
.ok
),
170 self
.pi
.st
.eq(inport
.st
),
171 inport
.ld
.eq(self
.pi
.ld
),
172 inport
.busy_o
.eq(self
.pi
.busy_o
),
173 inport
.addr_ok_o
.eq(self
.pi
.addr_ok_o
),
174 inport
.addr_exc_o
.eq(self
.pi
.addr_exc_o
),
178 yield self
.pi
.is_ld_i
179 yield self
.pi
.is_st_i
180 yield from self
.pi
.data_len
182 yield self
.pi
.go_die_i
183 yield from self
.pi
.addr
.ports()
184 yield self
.pi
.addr_ok_o
185 yield self
.pi
.addr_exc_o
187 yield from self
.pi
.ld
.ports()
188 yield from self
.pi
.st
.ports()
194 class TestMemoryPortInterface(Elaboratable
):
195 """TestMemoryPortInterface
197 This is a test class for simple verification of the LDSTCompUnit
198 and for the simple core, to be able to run unit tests rapidly and
199 with less other code in the way.
201 Versions of this which are *compatible* (conform with PortInterface)
202 will include augmented-Wishbone Bus versions, including ones that
203 connect to L1, L2, MMU etc. etc. however this is the "base lowest
204 possible version that complies with PortInterface".
207 def __init__(self
, regwid
=64, addrwid
=4):
208 self
.mem
= TestMemory(regwid
, addrwid
, granularity
=regwid
//8)
210 self
.addrwid
= addrwid
211 self
.pi
= LDSTPort(0, regwid
, addrwid
)
215 return log2_int(self
.mem
.regwid
//8)
217 def splitaddr(self
, addr
):
218 """split the address into top and bottom bits of the memory granularity
220 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
222 def connect_port(self
, inport
):
223 return self
.pi
.connect_port(inport
)
225 def elaborate(self
, platform
):
227 comb
, sync
= m
.d
.comb
, m
.d
.sync
229 # add TestMemory as submodule
230 m
.submodules
.mem
= self
.mem
232 # connect the ports as modules
233 m
.submodules
.port0
= self
.pi
235 # state-machine latches
236 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
237 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
238 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
239 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
241 # expand ld/st binary length/addr[:3] into unary bitmap
242 m
.submodules
.lenexp
= lenexp
= LenExpand(4, 8)
244 lds
= Signal(reset_less
=True)
245 sts
= Signal(reset_less
=True)
247 comb
+= lds
.eq(pi
.is_ld_i
& pi
.busy_o
) # ld-req signals
248 comb
+= sts
.eq(pi
.is_st_i
& pi
.busy_o
) # st-req signals
250 # convenience variables to reference the "picked" port
253 # and the memory ports
254 rdport
= self
.mem
.rdport
255 wrport
= self
.mem
.wrport
257 # Priority-Pickers pick one and only one request, capture its index.
258 # from that point on this code *only* "listens" to that port.
260 sync
+= adrok_l
.s
.eq(0)
261 comb
+= adrok_l
.r
.eq(0)
263 comb
+= ld_active
.s
.eq(1) # activate LD mode
265 comb
+= st_active
.s
.eq(1) # activate ST mode
267 # from this point onwards, with the port "picked", it stays picked
268 # until ld_active (or st_active) are de-asserted.
270 # if now in "LD" mode: wait for addr_ok, then send the address out
271 # to memory, acknowledge address, and send out LD data
272 with m
.If(ld_active
.q
):
273 # set up LenExpander with the LD len and lower bits of addr
274 lsbaddr
, msbaddr
= self
.splitaddr(ldport
.addr
.data
)
275 comb
+= lenexp
.len_i
.eq(ldport
.data_len
)
276 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
277 with m
.If(ldport
.addr
.ok
& adrok_l
.qn
):
278 comb
+= rdport
.addr
.eq(msbaddr
) # addr ok, send thru
279 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
280 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
282 # if now in "ST" mode: likewise do the same but with "ST"
283 # to memory, acknowledge address, and send out LD data
284 with m
.If(st_active
.q
):
285 # set up LenExpander with the ST len and lower bits of addr
286 lsbaddr
, msbaddr
= self
.splitaddr(stport
.addr
.data
)
287 comb
+= lenexp
.len_i
.eq(stport
.data_len
)
288 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
289 with m
.If(stport
.addr
.ok
):
290 comb
+= wrport
.addr
.eq(msbaddr
) # addr ok, send thru
291 with m
.If(adrok_l
.qn
):
292 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
293 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
295 # NOTE: in both these, below, the port itself takes care
296 # of de-asserting its "busy_o" signal, based on either ld.ok going
297 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
299 # for LD mode, when addr has been "ok'd", assume that (because this
300 # is a "Memory" test-class) the memory read data is valid.
301 comb
+= reset_l
.s
.eq(0)
302 comb
+= reset_l
.r
.eq(0)
303 with m
.If(ld_active
.q
& adrok_l
.q
):
304 # shift data down before pushing out. requires masking
305 # from the *byte*-expanded version of LenExpand output
306 lddata
= Signal(self
.regwid
, reset_less
=True)
307 # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
308 # and also handle the ready/stall/busy protocol
309 comb
+= lddata
.eq((rdport
.data
& lenexp
.rexp_o
) >>
311 comb
+= ldport
.ld
.data
.eq(lddata
) # put data out
312 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
313 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
315 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
316 with m
.If(st_active
.q
& stport
.st
.ok
):
317 # shift data up before storing. lenexp *bit* version of mask is
318 # passed straight through as byte-level "write-enable" lines.
319 stdata
= Signal(self
.regwid
, reset_less
=True)
320 comb
+= stdata
.eq(stport
.st
.data
<< (lenexp
.addr_i
*8))
321 # TODO: replace with link to LoadStoreUnitInterface.x_store_data
322 # and also handle the ready/stall/busy protocol
323 comb
+= wrport
.data
.eq(stdata
) # write st to mem
324 comb
+= wrport
.en
.eq(lenexp
.lexp_o
) # enable writes
325 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
327 # ugly hack, due to simultaneous addr req-go acknowledge
328 reset_delay
= Signal(reset_less
=True)
329 sync
+= reset_delay
.eq(reset_l
.q
)
330 with m
.If(reset_delay
):
331 comb
+= adrok_l
.r
.eq(1) # address reset
333 # after waiting one cycle (reset_l is "sync" mode), reset the port
334 with m
.If(reset_l
.q
):
335 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
336 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
337 comb
+= reset_l
.r
.eq(1) # clear reset
338 comb
+= adrok_l
.r
.eq(1) # address reset
343 for p
in self
.dports
:
347 def wait_busy(port
, no
=False):
349 busy
= yield port
.pi
.busy_o
350 print("busy", no
, busy
)
358 addr_ok
= yield port
.pi
.addr_ok_o
359 print("addrok", addr_ok
)
367 ldok
= yield port
.pi
.ld
.ok
374 def l0_cache_st(dut
, addr
, data
, datalen
):
378 # have to wait until not busy
379 yield from wait_busy(port1
, no
=False) # wait until not busy
381 # set up a ST on the port. address first:
382 yield port1
.pi
.is_st_i
.eq(1) # indicate ST
383 yield port1
.pi
.data_len
.eq(datalen
) # ST length (1/2/4/8)
385 yield port1
.pi
.addr
.data
.eq(addr
) # set address
386 yield port1
.pi
.addr
.ok
.eq(1) # set ok
387 yield from wait_addr(port1
) # wait until addr ok
388 # yield # not needed, just for checking
389 # yield # not needed, just for checking
390 # assert "ST" for one cycle (required by the API)
391 yield port1
.pi
.st
.data
.eq(data
)
392 yield port1
.pi
.st
.ok
.eq(1)
394 yield port1
.pi
.st
.ok
.eq(0)
396 # can go straight to reset.
397 yield port1
.pi
.is_st_i
.eq(0) # end
398 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
399 # yield from wait_busy(port1, False) # wait until not busy
402 def l0_cache_ld(dut
, addr
, datalen
, expected
):
407 # have to wait until not busy
408 yield from wait_busy(port1
, no
=False) # wait until not busy
410 # set up a LD on the port. address first:
411 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
412 yield port1
.pi
.data_len
.eq(datalen
) # LD length (1/2/4/8)
414 yield port1
.pi
.addr
.data
.eq(addr
) # set address
415 yield port1
.pi
.addr
.ok
.eq(1) # set ok
416 yield from wait_addr(port1
) # wait until addr ok
418 yield from wait_ldok(port1
) # wait until ld ok
419 data
= yield port1
.pi
.ld
.data
422 yield port1
.pi
.is_ld_i
.eq(0) # end
423 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
424 # yield from wait_busy(port1, no=False) # wait until not busy
429 def l0_cache_ldst(arg
, dut
):
435 yield from l0_cache_st(dut
, 0x2, data
, 2)
436 yield from l0_cache_st(dut
, 0x4, data2
, 2)
437 result
= yield from l0_cache_ld(dut
, 0x2, 2, data
)
438 result2
= yield from l0_cache_ld(dut
, 0x4, 2, data2
)
440 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
441 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
445 class TestPIMem(unittest
.TestCase
):
447 def test_pi_mem(self
):
449 dut
= TestMemoryPortInterface(regwid
=64)
450 #vl = rtlil.convert(dut, ports=dut.ports())
451 #with open("test_basic_l0_cache.il", "w") as f:
454 run_simulation(dut
, l0_cache_ldst(self
, dut
),
455 vcd_name
='test_pi_mem_basic.vcd')
458 if __name__
== '__main__':
459 unittest
.main(exit
=False)