src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34
  35 import unittest
  36
  37
  38 class PortInterface(RecordObject):
  39     """PortInterface
  40
  41     defines the interface - the API - that the LDSTCompUnit connects
  42     to.  note that this is NOT a "fire-and-forget" interface.  the
  43     LDSTCompUnit *must* be kept appraised that the request is in
  44     progress, and only when it has a 100% successful completion
  45     can the notification be given (busy dropped).
  46
  47     The interface FSM rules are as follows:
  48
  49     * if busy_o is asserted, a LD/ST is in progress.  further
  50       requests may not be made until busy_o is deasserted.
  51
  52     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  53       will immediately be asserted and remain asserted.
  54
  55     * addr.ok is to be asserted when the LD/ST address is known.
  56       addr.data is to be valid on the same cycle.
  57
  58       addr.ok and addr.data must REMAIN asserted until busy_o
  59       is de-asserted.  this ensures that there is no need
  60       for the L0 Cache/Buffer to have an additional address latch
  61       (because the LDSTCompUnit already has it)
  62
  63     * addr_ok_o (or exception.happened) must be waited for.  these will
  64       be asserted *only* for one cycle and one cycle only.
  65
  66     * exception.happened will be asserted if there is no chance that the
  67       memory request may be fulfilled.
  68
  69       busy_o is deasserted on the same cycle as exception.happened is asserted.
  70
  71     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  72       HUNDRED PERCENT guarantee that the memory request will be
  73       fulfilled.
  74
  75     * for a LD, ld.ok will be asserted - for only one clock cycle -
  76       at any point in the future that is acceptable to the underlying
  77       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  78
  79       busy_o is deasserted on the same cycle as ld.ok is asserted.
  80
  81     * for a ST, st.ok may be asserted only after addr_ok_o had been
  82       asserted, alongside valid st.data at the same time.  st.ok
  83       must only be asserted for one cycle.
  84
  85       the underlying Memory is REQUIRED to pick up that data and
  86       guarantee its delivery.  no back-acknowledgement is required.
  87
  88       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  89     """
  90
  91     def __init__(self, name=None, regwid=64, addrwid=48):
  92
  93         self._regwid = regwid
  94         self._addrwid = addrwid
  95
  96         RecordObject.__init__(self, name=name)
  97
  98         # distinguish op type (ld/st)
  99         self.is_ld_i = Signal(reset_less=True)
 100         self.is_st_i = Signal(reset_less=True)
 101
 102         # LD/ST data length (TODO: other things may be needed)
 103         self.data_len = Signal(4, reset_less=True)
 104
 105         # common signals
 106         self.busy_o = Signal(reset_less=True)     # do not use if busy
 107         self.go_die_i = Signal(reset_less=True)   # back to reset
 108         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 109         # addr is valid (TLB, L1 etc.)
 110         self.addr_ok_o = Signal(reset_less=True)
 111         self.exc_o = LDSTException("exc")
 112
 113         # LD/ST
 114         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 115         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 116
 117         # additional "modes"
 118         self.dcbz          = Signal()  # data cache block zero request
 119         self.nc            = Signal()  # no cacheing
 120         self.virt_mode     = Signal()  # virtual mode
 121         self.priv_mode     = Signal()  # privileged mode
 122
 123         # mmu
 124         self.mmu_done          = Signal() # keep for now
 125
 126         # dcache
 127         self.ldst_error        = Signal()
 128         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 129         self.cache_paradox     = Signal()
 130
 131     def connect_port(self, inport):
 132         print("connect_port", self, inport)
 133         return [self.is_ld_i.eq(inport.is_ld_i),
 134                 self.is_st_i.eq(inport.is_st_i),
 135                 self.data_len.eq(inport.data_len),
 136                 self.go_die_i.eq(inport.go_die_i),
 137                 self.addr.data.eq(inport.addr.data),
 138                 self.addr.ok.eq(inport.addr.ok),
 139                 self.st.eq(inport.st),
 140                 inport.ld.eq(self.ld),
 141                 inport.busy_o.eq(self.busy_o),
 142                 inport.addr_ok_o.eq(self.addr_ok_o),
 143                 inport.exc_o.eq(self.exc_o),
 144                 inport.mmu_done.eq(self.mmu_done),
 145                 inport.ldst_error.eq(self.ldst_error),
 146                 inport.cache_paradox.eq(self.cache_paradox)
 147                 ]
 148
 149
 150 class PortInterfaceBase(Elaboratable):
 151     """PortInterfaceBase
 152
 153     Base class for PortInterface-compliant Memory read/writers
 154     """
 155
 156     def __init__(self, regwid=64, addrwid=4):
 157         self.regwid = regwid
 158         self.addrwid = addrwid
 159         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 160
 161     @property
 162     def addrbits(self):
 163         return log2_int(self.regwid//8)
 164
 165     def splitaddr(self, addr):
 166         """split the address into top and bottom bits of the memory granularity
 167         """
 168         return addr[:self.addrbits], addr[self.addrbits:]
 169
 170     def connect_port(self, inport):
 171         return self.pi.connect_port(inport)
 172
 173     def set_wr_addr(self, m, addr, mask, misalign): pass
 174     def set_rd_addr(self, m, addr, mask, misalign): pass
 175     def set_wr_data(self, m, data, wen): pass
 176     def get_rd_data(self, m): pass
 177
 178     def elaborate(self, platform):
 179         m = Module()
 180         comb, sync = m.d.comb, m.d.sync
 181
 182         # state-machine latches
 183         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 184         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 185         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 186         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 187         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 188         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 189         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 190
 191         self.busy_l = busy_l
 192
 193         sync += st_done.s.eq(0)
 194         comb += st_done.r.eq(0)
 195         comb += st_active.r.eq(0)
 196         comb += ld_active.r.eq(0)
 197         comb += cyc_l.s.eq(0)
 198         comb += cyc_l.r.eq(0)
 199         comb += busy_l.s.eq(0)
 200         comb += busy_l.r.eq(0)
 201         sync += adrok_l.s.eq(0)
 202         comb += adrok_l.r.eq(0)
 203
 204         # expand ld/st binary length/addr[:3] into unary bitmap
 205         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 206
 207         lds = Signal(reset_less=True)
 208         sts = Signal(reset_less=True)
 209         pi = self.pi
 210         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 211         comb += sts.eq(pi.is_st_i)  # st-req signals
 212
 213         # detect busy "edge"
 214         busy_delay = Signal()
 215         busy_edge = Signal()
 216         sync += busy_delay.eq(pi.busy_o)
 217         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 218
 219         # misalignment detection: bits at end of lenexpand are set.
 220         # when using the L0CacheBuffer "data expander" which splits requests
 221         # into *two* PortInterfaces, this acts as a "safety check".
 222         misalign = Signal()
 223         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 224
 225         # activate mode: only on "edge"
 226         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 227         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 228
 229         # LD/ST requested activates "busy" (only if not already busy)
 230         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 231             comb += busy_l.s.eq(~busy_delay)
 232
 233         # if now in "LD" mode: wait for addr_ok, then send the address out
 234         # to memory, acknowledge address, and send out LD data
 235         with m.If(ld_active.q):
 236             # set up LenExpander with the LD len and lower bits of addr
 237             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 238             comb += lenexp.len_i.eq(pi.data_len)
 239             comb += lenexp.addr_i.eq(lsbaddr)
 240             with m.If(pi.addr.ok & adrok_l.qn):
 241                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign)
 242                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 243                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 244
 245         # if now in "ST" mode: likewise do the same but with "ST"
 246         # to memory, acknowledge address, and send out LD data
 247         with m.If(st_active.q):
 248             # set up LenExpander with the ST len and lower bits of addr
 249             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 250             comb += lenexp.len_i.eq(pi.data_len)
 251             comb += lenexp.addr_i.eq(lsbaddr)
 252             with m.If(pi.addr.ok):
 253                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign)
 254                 with m.If(adrok_l.qn):
 255                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 256                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 257
 258         # for LD mode, when addr has been "ok'd", assume that (because this
 259         # is a "Memory" test-class) the memory read data is valid.
 260         comb += reset_l.s.eq(0)
 261         comb += reset_l.r.eq(0)
 262         lddata = Signal(self.regwid, reset_less=True)
 263         data, ldok = self.get_rd_data(m)
 264         comb += lddata.eq((data & lenexp.rexp_o) >>
 265                           (lenexp.addr_i*8))
 266         with m.If(ld_active.q & adrok_l.q):
 267             # shift data down before pushing out.  requires masking
 268             # from the *byte*-expanded version of LenExpand output
 269             comb += pi.ld.data.eq(lddata)  # put data out
 270             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 271             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 272
 273         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 274         with m.If(st_active.q & pi.st.ok):
 275             # shift data up before storing.  lenexp *bit* version of mask is
 276             # passed straight through as byte-level "write-enable" lines.
 277             stdata = Signal(self.regwid, reset_less=True)
 278             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 279             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 280             # and also handle the ready/stall/busy protocol
 281             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 282             sync += st_done.s.eq(1)     # store done trigger
 283         with m.If(st_done.q):
 284             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 285
 286         # ugly hack, due to simultaneous addr req-go acknowledge
 287         reset_delay = Signal(reset_less=True)
 288         sync += reset_delay.eq(reset_l.q)
 289         with m.If(reset_delay):
 290             comb += adrok_l.r.eq(1)     # address reset
 291
 292         # after waiting one cycle (reset_l is "sync" mode), reset the port
 293         with m.If(reset_l.q):
 294             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 295             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 296             comb += reset_l.r.eq(1)     # clear reset
 297             comb += adrok_l.r.eq(1)     # address reset
 298             comb += st_done.r.eq(1)     # store done reset
 299
 300         # monitor for an exception, clear busy immediately
 301         with m.If(self.pi.exc_o.happened):
 302             comb += busy_l.r.eq(1)
 303
 304         # however ST needs one cycle before busy is reset
 305         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 306         with m.If(reset_l.s):
 307             comb += cyc_l.s.eq(1)
 308
 309         with m.If(cyc_l.q):
 310             comb += cyc_l.r.eq(1)
 311             comb += busy_l.r.eq(1)
 312
 313         # busy latch outputs to interface
 314         comb += pi.busy_o.eq(busy_l.q)
 315
 316         return m
 317
 318     def ports(self):
 319         yield from self.pi.ports()
 320
 321
 322 class TestMemoryPortInterface(PortInterfaceBase):
 323     """TestMemoryPortInterface
 324
 325     This is a test class for simple verification of the LDSTCompUnit
 326     and for the simple core, to be able to run unit tests rapidly and
 327     with less other code in the way.
 328
 329     Versions of this which are *compatible* (conform with PortInterface)
 330     will include augmented-Wishbone Bus versions, including ones that
 331     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 332     possible version that complies with PortInterface".
 333     """
 334
 335     def __init__(self, regwid=64, addrwid=4):
 336         super().__init__(regwid, addrwid)
 337         # hard-code memory addressing width to 6 bits
 338         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 339
 340     def set_wr_addr(self, m, addr, mask, misalign):
 341         lsbaddr, msbaddr = self.splitaddr(addr)
 342         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 343
 344     def set_rd_addr(self, m, addr, mask, misalign):
 345         lsbaddr, msbaddr = self.splitaddr(addr)
 346         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 347
 348     def set_wr_data(self, m, data, wen):
 349         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 350         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 351         return Const(1, 1)
 352
 353     def get_rd_data(self, m):
 354         return self.mem.rdport.data, Const(1, 1)
 355
 356     def elaborate(self, platform):
 357         m = super().elaborate(platform)
 358
 359         # add TestMemory as submodule
 360         m.submodules.mem = self.mem
 361
 362         return m
 363
 364     def ports(self):
 365         yield from super().ports()
 366         # TODO: memory ports