src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import verilog, rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23 from nmigen.hdl.rec import Record, Layout
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.decoder.power_enums import InternalOp
  28 from soc.regfile.regfile import ortreereduce
  29 from nmutil.util import treereduce
  30
  31 from soc.decoder.power_decoder2 import Data
  32 #from nmutil.picker import PriorityPicker
  33 from nmigen.lib.coding import PriorityEncoder
  34 from soc.scoreboard.addr_split import LDSTSplitter
  35 from soc.scoreboard.addr_match import LenExpand
  36
  37 # for testing purposes
  38 from soc.experiment.testmem import TestMemory # TODO: replace with TMLSUI
  39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
  40
  41 import unittest
  42
  43
  44 class PortInterface(RecordObject):
  45     """PortInterface
  46
  47     defines the interface - the API - that the LDSTCompUnit connects
  48     to.  note that this is NOT a "fire-and-forget" interface.  the
  49     LDSTCompUnit *must* be kept appraised that the request is in
  50     progress, and only when it has a 100% successful completion
  51     can the notification be given (busy dropped).
  52
  53     The interface FSM rules are as follows:
  54
  55     * if busy_o is asserted, a LD/ST is in progress.  further
  56       requests may not be made until busy_o is deasserted.
  57
  58     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  59       will immediately be asserted and remain asserted.
  60
  61     * addr.ok is to be asserted when the LD/ST address is known.
  62       addr.data is to be valid on the same cycle.
  63
  64       addr.ok and addr.data must REMAIN asserted until busy_o
  65       is de-asserted.  this ensures that there is no need
  66       for the L0 Cache/Buffer to have an additional address latch
  67       (because the LDSTCompUnit already has it)
  68
  69     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  70       be asserted *only* for one cycle and one cycle only.
  71
  72     * addr_exc_o will be asserted if there is no chance that the
  73       memory request may be fulfilled.
  74
  75       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  76
  77     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  78       HUNDRED PERCENT guarantee that the memory request will be
  79       fulfilled.
  80
  81     * for a LD, ld.ok will be asserted - for only one clock cycle -
  82       at any point in the future that is acceptable to the underlying
  83       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  84
  85       busy_o is deasserted on the same cycle as ld.ok is asserted.
  86
  87     * for a ST, st.ok may be asserted only after addr_ok_o had been
  88       asserted, alongside valid st.data at the same time.  st.ok
  89       must only be asserted for one cycle.
  90
  91       the underlying Memory is REQUIRED to pick up that data and
  92       guarantee its delivery.  no back-acknowledgement is required.
  93
  94       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  95     """
  96
  97     def __init__(self, name=None, regwid=64, addrwid=48):
  98
  99         self._regwid = regwid
 100         self._addrwid = addrwid
 101
 102         RecordObject.__init__(self, name=name)
 103
 104         # distinguish op type (ld/st)
 105         self.is_ld_i = Signal(reset_less=True)
 106         self.is_st_i = Signal(reset_less=True)
 107
 108         # LD/ST data length (TODO: other things may be needed)
 109         self.data_len = Signal(4, reset_less=True)
 110
 111         # common signals
 112         self.busy_o = Signal(reset_less=True)     # do not use if busy
 113         self.go_die_i = Signal(reset_less=True)   # back to reset
 114         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 115         # addr is valid (TLB, L1 etc.)
 116         self.addr_ok_o = Signal(reset_less=True)
 117         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 118
 119         # LD/ST
 120         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 121         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 122
 123     def connect_port(self, inport):
 124         print ("connect_port", self, inport)
 125         return [self.is_ld_i.eq(inport.is_ld_i),
 126                 self.is_st_i.eq(inport.is_st_i),
 127                 self.data_len.eq(inport.data_len),
 128                 self.go_die_i.eq(inport.go_die_i),
 129                 self.addr.data.eq(inport.addr.data),
 130                 self.addr.ok.eq(inport.addr.ok),
 131                 self.st.eq(inport.st),
 132                 inport.ld.eq(self.ld),
 133                 inport.busy_o.eq(self.busy_o),
 134                 inport.addr_ok_o.eq(self.addr_ok_o),
 135                 inport.addr_exc_o.eq(self.addr_exc_o),
 136                 ]
 137
 138
 139 class TestMemoryPortInterface(Elaboratable):
 140     """TestMemoryPortInterface
 141
 142     This is a test class for simple verification of the LDSTCompUnit
 143     and for the simple core, to be able to run unit tests rapidly and
 144     with less other code in the way.
 145
 146     Versions of this which are *compatible* (conform with PortInterface)
 147     will include augmented-Wishbone Bus versions, including ones that
 148     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 149     possible version that complies with PortInterface".
 150     """
 151
 152     def __init__(self, regwid=64, addrwid=4):
 153         # hard-code memory addressing width to 6 bits
 154         self.mem = TestMemory(regwid, 5, granularity=regwid//8,
 155                               init=False)
 156         self.regwid = regwid
 157         self.addrwid = addrwid
 158         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 159
 160     @property
 161     def addrbits(self):
 162         return log2_int(self.mem.regwid//8)
 163
 164     def splitaddr(self, addr):
 165         """split the address into top and bottom bits of the memory granularity
 166         """
 167         return addr[:self.addrbits], addr[self.addrbits:]
 168
 169     def connect_port(self, inport):
 170         return self.pi.connect_port(inport)
 171
 172     def elaborate(self, platform):
 173         m = Module()
 174         comb, sync = m.d.comb, m.d.sync
 175
 176         # add TestMemory as submodule
 177         m.submodules.mem = self.mem
 178
 179         # state-machine latches
 180         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 181         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 182         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 183         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 184         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 185         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 186         comb += cyc_l.s.eq(0)
 187         comb += cyc_l.r.eq(0)
 188
 189         # expand ld/st binary length/addr[:3] into unary bitmap
 190         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 191
 192         lds = Signal(reset_less=True)
 193         sts = Signal(reset_less=True)
 194         pi = self.pi
 195         comb += lds.eq(pi.is_ld_i & pi.busy_o)  # ld-req signals
 196         comb += sts.eq(pi.is_st_i & pi.busy_o)  # st-req signals
 197
 198         # convenience variables to reference the "picked" port
 199         ldport = pi
 200         stport = pi
 201         # and the memory ports
 202         rdport = self.mem.rdport
 203         wrport = self.mem.wrport
 204
 205         # Priority-Pickers pick one and only one request, capture its index.
 206         # from that point on this code *only* "listens" to that port.
 207
 208         sync += adrok_l.s.eq(0)
 209         comb += adrok_l.r.eq(0)
 210         with m.If(lds):
 211             comb += ld_active.s.eq(1)  # activate LD mode
 212         with m.Elif(sts):
 213             comb += st_active.s.eq(1)  # activate ST mode
 214
 215         # from this point onwards, with the port "picked", it stays picked
 216         # until ld_active (or st_active) are de-asserted.
 217
 218         # if now in "LD" mode: wait for addr_ok, then send the address out
 219         # to memory, acknowledge address, and send out LD data
 220         with m.If(ld_active.q):
 221             # set up LenExpander with the LD len and lower bits of addr
 222             lsbaddr, msbaddr = self.splitaddr(ldport.addr.data)
 223             comb += lenexp.len_i.eq(ldport.data_len)
 224             comb += lenexp.addr_i.eq(lsbaddr)
 225             with m.If(ldport.addr.ok & adrok_l.qn):
 226                 comb += rdport.addr.eq(msbaddr) # addr ok, send thru
 227                 comb += ldport.addr_ok_o.eq(1)  # acknowledge addr ok
 228                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 229
 230         # if now in "ST" mode: likewise do the same but with "ST"
 231         # to memory, acknowledge address, and send out LD data
 232         with m.If(st_active.q):
 233             # set up LenExpander with the ST len and lower bits of addr
 234             lsbaddr, msbaddr = self.splitaddr(stport.addr.data)
 235             comb += lenexp.len_i.eq(stport.data_len)
 236             comb += lenexp.addr_i.eq(lsbaddr)
 237             with m.If(stport.addr.ok):
 238                 comb += wrport.addr.eq(msbaddr)  # addr ok, send thru
 239                 with m.If(adrok_l.qn):
 240                     comb += stport.addr_ok_o.eq(1)  # acknowledge addr ok
 241                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 242
 243         # NOTE: in both these, below, the port itself takes care
 244         # of de-asserting its "busy_o" signal, based on either ld.ok going
 245         # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
 246
 247         # for LD mode, when addr has been "ok'd", assume that (because this
 248         # is a "Memory" test-class) the memory read data is valid.
 249         comb += reset_l.s.eq(0)
 250         comb += reset_l.r.eq(0)
 251         with m.If(ld_active.q & adrok_l.q):
 252             # shift data down before pushing out.  requires masking
 253             # from the *byte*-expanded version of LenExpand output
 254             lddata = Signal(self.regwid, reset_less=True)
 255             # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
 256             # and also handle the ready/stall/busy protocol
 257             comb += lddata.eq((rdport.data & lenexp.rexp_o) >>
 258                               (lenexp.addr_i*8))
 259             comb += ldport.ld.data.eq(lddata)  # put data out
 260             comb += ldport.ld.ok.eq(1)           # indicate data valid
 261             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 262
 263         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 264         with m.If(st_active.q & stport.st.ok):
 265             # shift data up before storing.  lenexp *bit* version of mask is
 266             # passed straight through as byte-level "write-enable" lines.
 267             stdata = Signal(self.regwid, reset_less=True)
 268             comb += stdata.eq(stport.st.data << (lenexp.addr_i*8))
 269             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 270             # and also handle the ready/stall/busy protocol
 271             comb += wrport.data.eq(stdata)  # write st to mem
 272             comb += wrport.en.eq(lenexp.lexp_o) # enable writes
 273             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 274
 275         # ugly hack, due to simultaneous addr req-go acknowledge
 276         reset_delay = Signal(reset_less=True)
 277         sync += reset_delay.eq(reset_l.q)
 278         with m.If(reset_delay):
 279             comb += adrok_l.r.eq(1)     # address reset
 280
 281         # after waiting one cycle (reset_l is "sync" mode), reset the port
 282         with m.If(reset_l.q):
 283             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 284             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 285             comb += reset_l.r.eq(1)     # clear reset
 286             comb += adrok_l.r.eq(1)     # address reset
 287
 288         # LD/ST requested activates "busy"
 289         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 290             comb += busy_l.s.eq(1)
 291
 292         # monitor for an exception or the completion of LD.
 293         with m.If(self.pi.addr_exc_o):
 294             comb += busy_l.r.eq(1)
 295
 296         # however ST needs one cycle before busy is reset
 297         with m.If(self.pi.st.ok | self.pi.ld.ok):
 298             comb += cyc_l.s.eq(1)
 299
 300         with m.If(cyc_l.q):
 301             comb += cyc_l.r.eq(1)
 302             comb += busy_l.r.eq(1)
 303
 304         # busy latch outputs to interface
 305         comb += self.pi.busy_o.eq(busy_l.q)
 306
 307         return m
 308
 309     def ports(self):
 310         for p in self.dports:
 311             yield from p.ports()
 312
 313
 314