src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34 from nmutil.util import Display
  35 from collections import namedtuple
  36 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"]) # used in unit tests
  37
  38 import unittest
  39
  40
  41 class PortInterface(RecordObject):
  42     """PortInterface
  43
  44     defines the interface - the API - that the LDSTCompUnit connects
  45     to.  note that this is NOT a "fire-and-forget" interface.  the
  46     LDSTCompUnit *must* be kept appraised that the request is in
  47     progress, and only when it has a 100% successful completion
  48     can the notification be given (busy dropped).
  49
  50     The interface FSM rules are as follows:
  51
  52     * if busy_o is asserted, a LD/ST is in progress.  further
  53       requests may not be made until busy_o is deasserted.
  54
  55     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  56       will immediately be asserted and remain asserted.
  57
  58     * addr.ok is to be asserted when the LD/ST address is known.
  59       addr.data is to be valid on the same cycle.
  60
  61       addr.ok and addr.data must REMAIN asserted until busy_o
  62       is de-asserted.  this ensures that there is no need
  63       for the L0 Cache/Buffer to have an additional address latch
  64       (because the LDSTCompUnit already has it)
  65
  66     * addr_ok_o (or exception.happened) must be waited for.  these will
  67       be asserted *only* for one cycle and one cycle only.
  68
  69     * exception.happened will be asserted if there is no chance that the
  70       memory request may be fulfilled.
  71
  72       busy_o is deasserted on the same cycle as exception.happened is asserted.
  73
  74     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  75       HUNDRED PERCENT guarantee that the memory request will be
  76       fulfilled.
  77
  78     * for a LD, ld.ok will be asserted - for only one clock cycle -
  79       at any point in the future that is acceptable to the underlying
  80       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  81
  82       busy_o is deasserted on the same cycle as ld.ok is asserted.
  83
  84     * for a ST, st.ok may be asserted only after addr_ok_o had been
  85       asserted, alongside valid st.data at the same time.  st.ok
  86       must only be asserted for one cycle.
  87
  88       the underlying Memory is REQUIRED to pick up that data and
  89       guarantee its delivery.  no back-acknowledgement is required.
  90
  91       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  92     """
  93
  94     def __init__(self, name=None, regwid=64, addrwid=48):
  95
  96         self._regwid = regwid
  97         self._addrwid = addrwid
  98
  99         RecordObject.__init__(self, name=name)
 100
 101         # distinguish op type (ld/st)
 102         self.is_ld_i    = Signal(reset_less=True)
 103         self.is_st_i    = Signal(reset_less=True)
 104
 105         # LD/ST data length (TODO: other things may be needed)
 106         self.data_len = Signal(4, reset_less=True)
 107
 108         # common signals
 109         self.busy_o = Signal(reset_less=True)     # do not use if busy
 110         self.go_die_i = Signal(reset_less=True)   # back to reset
 111         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 112         # addr is valid (TLB, L1 etc.)
 113         self.addr_ok_o = Signal(reset_less=True)
 114         self.exc_o = LDSTException("exc")
 115
 116         # LD/ST
 117         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 118         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 119
 120         # additional "modes"
 121         self.is_nc         = Signal()  # no cacheing
 122
 123         #only priv_mode = not msr_pr is used currently
 124         # TODO: connect signals
 125         self.virt_mode  = Signal() # ctrl.msr(MSR_DR);
 126         self.priv_mode  = Signal() # not ctrl.msr(MSR_PR);
 127         self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
 128
 129         self.is_dcbz_i     = Signal(reset_less=True)
 130
 131         # mmu
 132         self.mmu_done          = Signal() # keep for now
 133
 134         # dcache
 135         self.ldst_error        = Signal()
 136         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 137         self.cache_paradox     = Signal()
 138
 139     def connect_port(self, inport):
 140         print("connect_port", self, inport)
 141         return [self.is_ld_i.eq(inport.is_ld_i),
 142                 self.is_st_i.eq(inport.is_st_i),
 143                 self.is_nc.eq(inport.is_nc),
 144                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 145                 self.data_len.eq(inport.data_len),
 146                 self.go_die_i.eq(inport.go_die_i),
 147                 self.addr.data.eq(inport.addr.data),
 148                 self.addr.ok.eq(inport.addr.ok),
 149                 self.st.eq(inport.st),
 150                 self.virt_mode.eq(inport.virt_mode),
 151                 self.priv_mode.eq(inport.priv_mode),
 152                 self.mode_32bit.eq(inport.mode_32bit),
 153                 inport.ld.eq(self.ld),
 154                 inport.busy_o.eq(self.busy_o),
 155                 inport.addr_ok_o.eq(self.addr_ok_o),
 156                 inport.exc_o.eq(self.exc_o),
 157                 inport.mmu_done.eq(self.mmu_done),
 158                 inport.ldst_error.eq(self.ldst_error),
 159                 inport.cache_paradox.eq(self.cache_paradox)
 160                 ]
 161
 162
 163 class PortInterfaceBase(Elaboratable):
 164     """PortInterfaceBase
 165
 166     Base class for PortInterface-compliant Memory read/writers
 167     """
 168
 169     def __init__(self, regwid=64, addrwid=4):
 170         self.regwid = regwid
 171         self.addrwid = addrwid
 172         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 173
 174     @property
 175     def addrbits(self):
 176         return log2_int(self.regwid//8)
 177
 178     def splitaddr(self, addr):
 179         """split the address into top and bottom bits of the memory granularity
 180         """
 181         return addr[:self.addrbits], addr[self.addrbits:]
 182
 183     def connect_port(self, inport):
 184         return self.pi.connect_port(inport)
 185
 186     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass
 187     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 188     def set_wr_data(self, m, data, wen): pass
 189     def get_rd_data(self, m): pass
 190
 191     def elaborate(self, platform):
 192         m = Module()
 193         comb, sync = m.d.comb, m.d.sync
 194
 195         # state-machine latches
 196         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 197         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 198         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 199         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 200         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 201         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 202         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 203
 204         self.busy_l = busy_l
 205
 206         sync += st_done.s.eq(0)
 207         comb += st_done.r.eq(0)
 208         comb += st_active.r.eq(0)
 209         comb += ld_active.r.eq(0)
 210         comb += cyc_l.s.eq(0)
 211         comb += cyc_l.r.eq(0)
 212         comb += busy_l.s.eq(0)
 213         comb += busy_l.r.eq(0)
 214         sync += adrok_l.s.eq(0)
 215         comb += adrok_l.r.eq(0)
 216
 217         # expand ld/st binary length/addr[:3] into unary bitmap
 218         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 219
 220         lds = Signal(reset_less=True)
 221         sts = Signal(reset_less=True)
 222         pi = self.pi
 223         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 224         comb += sts.eq(pi.is_st_i)  # st-req signals
 225         pr = ~pi.priv_mode
 226
 227         # detect busy "edge"
 228         busy_delay = Signal()
 229         busy_edge = Signal()
 230         sync += busy_delay.eq(pi.busy_o)
 231         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 232
 233         # misalignment detection: bits at end of lenexpand are set.
 234         # when using the L0CacheBuffer "data expander" which splits requests
 235         # into *two* PortInterfaces, this acts as a "safety check".
 236         misalign = Signal()
 237         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 238
 239
 240         # activate mode: only on "edge"
 241         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 242         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 243
 244         # LD/ST requested activates "busy" (only if not already busy)
 245         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 246             comb += busy_l.s.eq(~busy_delay)
 247             with m.If(self.pi.exc_o.happened):
 248                 sync += Display("fast exception")
 249
 250         # if now in "LD" mode: wait for addr_ok, then send the address out
 251         # to memory, acknowledge address, and send out LD data
 252         with m.If(ld_active.q):
 253             # set up LenExpander with the LD len and lower bits of addr
 254             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 255             comb += lenexp.len_i.eq(pi.data_len)
 256             comb += lenexp.addr_i.eq(lsbaddr)
 257             with m.If(pi.addr.ok & adrok_l.qn):
 258                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 259                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 260                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 261
 262         # if now in "ST" mode: likewise do the same but with "ST"
 263         # to memory, acknowledge address, and send out LD data
 264         with m.If(st_active.q):
 265             # set up LenExpander with the ST len and lower bits of addr
 266             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 267             comb += lenexp.len_i.eq(pi.data_len)
 268             comb += lenexp.addr_i.eq(lsbaddr)
 269             with m.If(pi.addr.ok):
 270                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
 271                                  pi.is_dcbz_i)
 272                 with m.If(adrok_l.qn & self.pi.exc_o.happened==0):
 273                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 274                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 275
 276         # for LD mode, when addr has been "ok'd", assume that (because this
 277         # is a "Memory" test-class) the memory read data is valid.
 278         comb += reset_l.s.eq(0)
 279         comb += reset_l.r.eq(0)
 280         lddata = Signal(self.regwid, reset_less=True)
 281         data, ldok = self.get_rd_data(m)
 282         comb += lddata.eq((data & lenexp.rexp_o) >>
 283                           (lenexp.addr_i*8))
 284         with m.If(ld_active.q & adrok_l.q):
 285             # shift data down before pushing out.  requires masking
 286             # from the *byte*-expanded version of LenExpand output
 287             comb += pi.ld.data.eq(lddata)  # put data out
 288             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 289             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 290
 291         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 292         sync += st_done.s.eq(0)     # store done trigger
 293         with m.If(st_active.q & pi.st.ok):
 294             # shift data up before storing.  lenexp *bit* version of mask is
 295             # passed straight through as byte-level "write-enable" lines.
 296             stdata = Signal(self.regwid, reset_less=True)
 297             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 298             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 299             # and also handle the ready/stall/busy protocol
 300             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 301             sync += st_done.s.eq(~self.pi.exc_o.happened) # store done trigger
 302         with m.If(st_done.q):
 303             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 304
 305         # ugly hack, due to simultaneous addr req-go acknowledge
 306         reset_delay = Signal(reset_less=True)
 307         sync += reset_delay.eq(reset_l.q)
 308         with m.If(reset_delay):
 309             comb += adrok_l.r.eq(1)     # address reset
 310
 311         # after waiting one cycle (reset_l is "sync" mode), reset the port
 312         with m.If(reset_l.q):
 313             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 314             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 315             comb += reset_l.r.eq(1)     # clear reset
 316             comb += adrok_l.r.eq(1)     # address reset
 317             comb += st_done.r.eq(1)     # store done reset
 318
 319         # monitor for an exception, clear busy immediately
 320         with m.If(self.pi.exc_o.happened):
 321             comb += busy_l.r.eq(1)
 322             comb += reset_l.s.eq(1) # also reset whole unit
 323
 324         # however ST needs one cycle before busy is reset
 325         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 326         with m.If(reset_l.s):
 327             comb += cyc_l.s.eq(1)
 328
 329         with m.If(cyc_l.q):
 330             comb += cyc_l.r.eq(1)
 331             comb += busy_l.r.eq(1)
 332
 333         # busy latch outputs to interface
 334         if hasattr(self, "external_busy"):
 335             # when there is an extra (external) busy, include that here.
 336             # this is used e.g. in LoadStore1 when an instruction fault
 337             # is being processed (instr_fault) and stops Load/Store requests
 338             # from being made until it's done
 339             comb += pi.busy_o.eq(busy_l.q | self.external_busy(m))
 340         else:
 341             comb += pi.busy_o.eq(busy_l.q)
 342
 343         return m
 344
 345     def ports(self):
 346         yield from self.pi.ports()
 347
 348
 349 class TestMemoryPortInterface(PortInterfaceBase):
 350     """TestMemoryPortInterface
 351
 352     This is a test class for simple verification of the LDSTCompUnit
 353     and for the simple core, to be able to run unit tests rapidly and
 354     with less other code in the way.
 355
 356     Versions of this which are *compatible* (conform with PortInterface)
 357     will include augmented-Wishbone Bus versions, including ones that
 358     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 359     possible version that complies with PortInterface".
 360     """
 361
 362     def __init__(self, regwid=64, addrwid=4):
 363         super().__init__(regwid, addrwid)
 364         # hard-code memory addressing width to 6 bits
 365         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 366
 367     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
 368         lsbaddr, msbaddr = self.splitaddr(addr)
 369         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 370
 371     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 372         lsbaddr, msbaddr = self.splitaddr(addr)
 373         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 374
 375     def set_wr_data(self, m, data, wen):
 376         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 377         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 378         return Const(1, 1)
 379
 380     def get_rd_data(self, m):
 381         return self.mem.rdport.data, Const(1, 1)
 382
 383     def elaborate(self, platform):
 384         m = super().elaborate(platform)
 385
 386         # add TestMemory as submodule
 387         m.submodules.mem = self.mem
 388
 389         return m
 390
 391     def ports(self):
 392         yield from super().ports()
 393         # TODO: memory ports