3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
, Settle
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
23 from nmigen
.hdl
.rec
import Record
, Layout
25 from nmutil
.latch
import SRLatch
, latchregister
26 from soc
.decoder
.power_decoder2
import Data
27 from soc
.decoder
.power_enums
import InternalOp
28 from soc
.regfile
.regfile
import ortreereduce
29 from nmutil
.util
import treereduce
31 from soc
.decoder
.power_decoder2
import Data
32 #from nmutil.picker import PriorityPicker
33 from nmigen
.lib
.coding
import PriorityEncoder
34 from soc
.scoreboard
.addr_split
import LDSTSplitter
35 from soc
.scoreboard
.addr_match
import LenExpand
37 # for testing purposes
38 from soc
.experiment
.testmem
import TestMemory
# TODO: replace with TMLSUI
39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
44 class PortInterface(RecordObject
):
47 defines the interface - the API - that the LDSTCompUnit connects
48 to. note that this is NOT a "fire-and-forget" interface. the
49 LDSTCompUnit *must* be kept appraised that the request is in
50 progress, and only when it has a 100% successful completion
51 can the notification be given (busy dropped).
53 The interface FSM rules are as follows:
55 * if busy_o is asserted, a LD/ST is in progress. further
56 requests may not be made until busy_o is deasserted.
58 * only one of is_ld_i or is_st_i may be asserted. busy_o
59 will immediately be asserted and remain asserted.
61 * addr.ok is to be asserted when the LD/ST address is known.
62 addr.data is to be valid on the same cycle.
64 addr.ok and addr.data must REMAIN asserted until busy_o
65 is de-asserted. this ensures that there is no need
66 for the L0 Cache/Buffer to have an additional address latch
67 (because the LDSTCompUnit already has it)
69 * addr_ok_o (or addr_exc_o) must be waited for. these will
70 be asserted *only* for one cycle and one cycle only.
72 * addr_exc_o will be asserted if there is no chance that the
73 memory request may be fulfilled.
75 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
77 * conversely: addr_ok_o must *ONLY* be asserted if there is a
78 HUNDRED PERCENT guarantee that the memory request will be
81 * for a LD, ld.ok will be asserted - for only one clock cycle -
82 at any point in the future that is acceptable to the underlying
83 Memory subsystem. the recipient MUST latch ld.data on that cycle.
85 busy_o is deasserted on the same cycle as ld.ok is asserted.
87 * for a ST, st.ok may be asserted only after addr_ok_o had been
88 asserted, alongside valid st.data at the same time. st.ok
89 must only be asserted for one cycle.
91 the underlying Memory is REQUIRED to pick up that data and
92 guarantee its delivery. no back-acknowledgement is required.
94 busy_o is deasserted on the cycle AFTER st.ok is asserted.
97 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
100 self
._addrwid
= addrwid
102 RecordObject
.__init
__(self
, name
=name
)
104 name
= name
or "port0"
106 # distinguish op type (ld/st)
107 self
.is_ld_i
= Signal(reset_less
=True, name
=f
"{name}_is_ld_i")
108 self
.is_st_i
= Signal(reset_less
=True, name
=f
"{name}_is_st_i")
110 # LD/ST data length (TODO: other things may be needed)
111 self
.data_len
= Signal(4, reset_less
=True, name
=f
"{name}_data_len")
116 self
.busy_o
= Signal(reset_less
=True, name
=f
"{name}_busy_o")
118 self
.go_die_i
= Signal(reset_less
=True, name
=f
"{name}_go_die_i")
120 self
.addr
= Data(addrwid
, f
"{name}_addr_i") # addr/addr-ok
121 # addr is valid (TLB, L1 etc.)
122 self
.addr_ok_o
= Signal(reset_less
=True, name
=f
"{name}_addr_ok_o")
123 # TODO, "type" of exception
124 self
.addr_exc_o
= Signal(reset_less
=True, name
=f
"{name}_addr_exc_o")
127 self
.ld
= Data(regwid
, f
"{name}_ld_data_o") # ok to be set by L0 Cache/Buf
128 self
.st
= Data(regwid
, f
"{name}_st_data_i") # ok to be set by CompUnit
131 class LDSTPort(Elaboratable
):
132 def __init__(self
, idx
, regwid
=64, addrwid
=48):
133 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
135 def elaborate(self
, platform
):
137 comb
, sync
= m
.d
.comb
, m
.d
.sync
140 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
141 m
.submodules
.cyc_l
= cyc_l
= SRLatch(True, name
="cyc")
142 comb
+= cyc_l
.s
.eq(0)
143 comb
+= cyc_l
.r
.eq(0)
145 # this is a little weird: we let the L0Cache/Buffer set
146 # the outputs: this module just monitors "state".
148 # LD/ST requested activates "busy"
149 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
150 comb
+= busy_l
.s
.eq(1)
152 # monitor for an exception or the completion of LD.
153 with m
.If(self
.pi
.addr_exc_o
):
154 comb
+= busy_l
.r
.eq(1)
156 # however ST needs one cycle before busy is reset
157 with m
.If(self
.pi
.st
.ok | self
.pi
.ld
.ok
):
158 comb
+= cyc_l
.s
.eq(1)
161 comb
+= cyc_l
.r
.eq(1)
162 comb
+= busy_l
.r
.eq(1)
164 # busy latch outputs to interface
165 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
169 def connect_port(self
, inport
):
170 print ("connect_port", self
.pi
, inport
)
171 return [self
.pi
.is_ld_i
.eq(inport
.is_ld_i
),
172 self
.pi
.is_st_i
.eq(inport
.is_st_i
),
173 self
.pi
.data_len
.eq(inport
.data_len
),
174 self
.pi
.go_die_i
.eq(inport
.go_die_i
),
175 self
.pi
.addr
.data
.eq(inport
.addr
.data
),
176 self
.pi
.addr
.ok
.eq(inport
.addr
.ok
),
177 self
.pi
.st
.eq(inport
.st
),
178 inport
.ld
.eq(self
.pi
.ld
),
179 inport
.busy_o
.eq(self
.pi
.busy_o
),
180 inport
.addr_ok_o
.eq(self
.pi
.addr_ok_o
),
181 inport
.addr_exc_o
.eq(self
.pi
.addr_exc_o
),
185 yield self
.pi
.is_ld_i
186 yield self
.pi
.is_st_i
187 yield from self
.pi
.data_len
189 yield self
.pi
.go_die_i
190 yield from self
.pi
.addr
.ports()
191 yield self
.pi
.addr_ok_o
192 yield self
.pi
.addr_exc_o
194 yield from self
.pi
.ld
.ports()
195 yield from self
.pi
.st
.ports()
201 class TestMemoryPortInterface(Elaboratable
):
202 """TestMemoryPortInterface
204 This is a test class for simple verification of the LDSTCompUnit
205 and for the simple core, to be able to run unit tests rapidly and
206 with less other code in the way.
208 Versions of this which are *compatible* (conform with PortInterface)
209 will include augmented-Wishbone Bus versions, including ones that
210 connect to L1, L2, MMU etc. etc. however this is the "base lowest
211 possible version that complies with PortInterface".
214 def __init__(self
, regwid
=64, addrwid
=4):
215 self
.mem
= TestMemory(regwid
, addrwid
, granularity
=regwid
//8)
217 self
.addrwid
= addrwid
218 self
.pi
= LDSTPort(0, regwid
, addrwid
)
222 return log2_int(self
.mem
.regwid
//8)
224 def splitaddr(self
, addr
):
225 """split the address into top and bottom bits of the memory granularity
227 return addr
[:self
.addrbits
], addr
[self
.addrbits
:]
229 def connect_port(self
, inport
):
230 return self
.pi
.connect_port(inport
)
232 def elaborate(self
, platform
):
234 comb
, sync
= m
.d
.comb
, m
.d
.sync
236 # add TestMemory as submodule
237 m
.submodules
.mem
= self
.mem
239 # connect the ports as modules
240 m
.submodules
.port0
= self
.pi
242 # state-machine latches
243 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
244 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
245 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
246 m
.submodules
.adrok_l
= adrok_l
= SRLatch(False, name
="addr_acked")
248 # expand ld/st binary length/addr[:3] into unary bitmap
249 m
.submodules
.lenexp
= lenexp
= LenExpand(4, 8)
251 lds
= Signal(reset_less
=True)
252 sts
= Signal(reset_less
=True)
254 comb
+= lds
.eq(pi
.is_ld_i
& pi
.busy_o
) # ld-req signals
255 comb
+= sts
.eq(pi
.is_st_i
& pi
.busy_o
) # st-req signals
257 # convenience variables to reference the "picked" port
260 # and the memory ports
261 rdport
= self
.mem
.rdport
262 wrport
= self
.mem
.wrport
264 # Priority-Pickers pick one and only one request, capture its index.
265 # from that point on this code *only* "listens" to that port.
267 sync
+= adrok_l
.s
.eq(0)
268 comb
+= adrok_l
.r
.eq(0)
270 comb
+= ld_active
.s
.eq(1) # activate LD mode
272 comb
+= st_active
.s
.eq(1) # activate ST mode
274 # from this point onwards, with the port "picked", it stays picked
275 # until ld_active (or st_active) are de-asserted.
277 # if now in "LD" mode: wait for addr_ok, then send the address out
278 # to memory, acknowledge address, and send out LD data
279 with m
.If(ld_active
.q
):
280 # set up LenExpander with the LD len and lower bits of addr
281 lsbaddr
, msbaddr
= self
.splitaddr(ldport
.addr
.data
)
282 comb
+= lenexp
.len_i
.eq(ldport
.data_len
)
283 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
284 with m
.If(ldport
.addr
.ok
& adrok_l
.qn
):
285 comb
+= rdport
.addr
.eq(msbaddr
) # addr ok, send thru
286 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
287 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
289 # if now in "ST" mode: likewise do the same but with "ST"
290 # to memory, acknowledge address, and send out LD data
291 with m
.If(st_active
.q
):
292 # set up LenExpander with the ST len and lower bits of addr
293 lsbaddr
, msbaddr
= self
.splitaddr(stport
.addr
.data
)
294 comb
+= lenexp
.len_i
.eq(stport
.data_len
)
295 comb
+= lenexp
.addr_i
.eq(lsbaddr
)
296 with m
.If(stport
.addr
.ok
):
297 comb
+= wrport
.addr
.eq(msbaddr
) # addr ok, send thru
298 with m
.If(adrok_l
.qn
):
299 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
300 sync
+= adrok_l
.s
.eq(1) # and pull "ack" latch
302 # NOTE: in both these, below, the port itself takes care
303 # of de-asserting its "busy_o" signal, based on either ld.ok going
304 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
306 # for LD mode, when addr has been "ok'd", assume that (because this
307 # is a "Memory" test-class) the memory read data is valid.
308 comb
+= reset_l
.s
.eq(0)
309 comb
+= reset_l
.r
.eq(0)
310 with m
.If(ld_active
.q
& adrok_l
.q
):
311 # shift data down before pushing out. requires masking
312 # from the *byte*-expanded version of LenExpand output
313 lddata
= Signal(self
.regwid
, reset_less
=True)
314 # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
315 # and also handle the ready/stall/busy protocol
316 comb
+= lddata
.eq((rdport
.data
& lenexp
.rexp_o
) >>
318 comb
+= ldport
.ld
.data
.eq(lddata
) # put data out
319 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
320 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
322 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
323 with m
.If(st_active
.q
& stport
.st
.ok
):
324 # shift data up before storing. lenexp *bit* version of mask is
325 # passed straight through as byte-level "write-enable" lines.
326 stdata
= Signal(self
.regwid
, reset_less
=True)
327 comb
+= stdata
.eq(stport
.st
.data
<< (lenexp
.addr_i
*8))
328 # TODO: replace with link to LoadStoreUnitInterface.x_store_data
329 # and also handle the ready/stall/busy protocol
330 comb
+= wrport
.data
.eq(stdata
) # write st to mem
331 comb
+= wrport
.en
.eq(lenexp
.lexp_o
) # enable writes
332 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
334 # ugly hack, due to simultaneous addr req-go acknowledge
335 reset_delay
= Signal(reset_less
=True)
336 sync
+= reset_delay
.eq(reset_l
.q
)
337 with m
.If(reset_delay
):
338 comb
+= adrok_l
.r
.eq(1) # address reset
340 # after waiting one cycle (reset_l is "sync" mode), reset the port
341 with m
.If(reset_l
.q
):
342 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
343 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
344 comb
+= reset_l
.r
.eq(1) # clear reset
345 comb
+= adrok_l
.r
.eq(1) # address reset
350 for p
in self
.dports
:
354 def wait_busy(port
, no
=False):
356 busy
= yield port
.pi
.busy_o
357 print("busy", no
, busy
)
365 addr_ok
= yield port
.pi
.addr_ok_o
366 print("addrok", addr_ok
)
374 ldok
= yield port
.pi
.ld
.ok
381 def l0_cache_st(dut
, addr
, data
, datalen
):
385 # have to wait until not busy
386 yield from wait_busy(port1
, no
=False) # wait until not busy
388 # set up a ST on the port. address first:
389 yield port1
.pi
.is_st_i
.eq(1) # indicate ST
390 yield port1
.pi
.data_len
.eq(datalen
) # ST length (1/2/4/8)
392 yield port1
.pi
.addr
.data
.eq(addr
) # set address
393 yield port1
.pi
.addr
.ok
.eq(1) # set ok
394 yield from wait_addr(port1
) # wait until addr ok
395 # yield # not needed, just for checking
396 # yield # not needed, just for checking
397 # assert "ST" for one cycle (required by the API)
398 yield port1
.pi
.st
.data
.eq(data
)
399 yield port1
.pi
.st
.ok
.eq(1)
401 yield port1
.pi
.st
.ok
.eq(0)
403 # can go straight to reset.
404 yield port1
.pi
.is_st_i
.eq(0) # end
405 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
406 # yield from wait_busy(port1, False) # wait until not busy
409 def l0_cache_ld(dut
, addr
, datalen
, expected
):
414 # have to wait until not busy
415 yield from wait_busy(port1
, no
=False) # wait until not busy
417 # set up a LD on the port. address first:
418 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
419 yield port1
.pi
.data_len
.eq(datalen
) # LD length (1/2/4/8)
421 yield port1
.pi
.addr
.data
.eq(addr
) # set address
422 yield port1
.pi
.addr
.ok
.eq(1) # set ok
423 yield from wait_addr(port1
) # wait until addr ok
425 yield from wait_ldok(port1
) # wait until ld ok
426 data
= yield port1
.pi
.ld
.data
429 yield port1
.pi
.is_ld_i
.eq(0) # end
430 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
431 # yield from wait_busy(port1, no=False) # wait until not busy
436 def l0_cache_ldst(arg
, dut
):
442 yield from l0_cache_st(dut
, 0x2, data
, 2)
443 yield from l0_cache_st(dut
, 0x4, data2
, 2)
444 result
= yield from l0_cache_ld(dut
, 0x2, 2, data
)
445 result2
= yield from l0_cache_ld(dut
, 0x4, 2, data2
)
447 arg
.assertEqual(data
, result
, "data %x != %x" % (result
, data
))
448 arg
.assertEqual(data2
, result2
, "data2 %x != %x" % (result2
, data2
))
452 class TestPIMem(unittest
.TestCase
):
454 def test_pi_mem(self
):
456 dut
= TestMemoryPortInterface(regwid
=64)
457 #vl = rtlil.convert(dut, ports=dut.ports())
458 #with open("test_basic_l0_cache.il", "w") as f:
461 run_simulation(dut
, l0_cache_ldst(self
, dut
),
462 vcd_name
='test_pi_mem_basic.vcd')
465 if __name__
== '__main__':
466 unittest
.main(exit
=False)