src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23
  24 from nmutil.latch import SRLatch, latchregister
  25 from soc.decoder.power_decoder2 import Data
  26 from soc.scoreboard.addr_match import LenExpand
  27
  28 # for testing purposes
  29 from soc.experiment.testmem import TestMemory
  30
  31 import unittest
  32
  33
  34 class PortInterface(RecordObject):
  35     """PortInterface
  36
  37     defines the interface - the API - that the LDSTCompUnit connects
  38     to.  note that this is NOT a "fire-and-forget" interface.  the
  39     LDSTCompUnit *must* be kept appraised that the request is in
  40     progress, and only when it has a 100% successful completion
  41     can the notification be given (busy dropped).
  42
  43     The interface FSM rules are as follows:
  44
  45     * if busy_o is asserted, a LD/ST is in progress.  further
  46       requests may not be made until busy_o is deasserted.
  47
  48     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  49       will immediately be asserted and remain asserted.
  50
  51     * addr.ok is to be asserted when the LD/ST address is known.
  52       addr.data is to be valid on the same cycle.
  53
  54       addr.ok and addr.data must REMAIN asserted until busy_o
  55       is de-asserted.  this ensures that there is no need
  56       for the L0 Cache/Buffer to have an additional address latch
  57       (because the LDSTCompUnit already has it)
  58
  59     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  60       be asserted *only* for one cycle and one cycle only.
  61
  62     * addr_exc_o will be asserted if there is no chance that the
  63       memory request may be fulfilled.
  64
  65       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  66
  67     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  68       HUNDRED PERCENT guarantee that the memory request will be
  69       fulfilled.
  70
  71     * for a LD, ld.ok will be asserted - for only one clock cycle -
  72       at any point in the future that is acceptable to the underlying
  73       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  74
  75       busy_o is deasserted on the same cycle as ld.ok is asserted.
  76
  77     * for a ST, st.ok may be asserted only after addr_ok_o had been
  78       asserted, alongside valid st.data at the same time.  st.ok
  79       must only be asserted for one cycle.
  80
  81       the underlying Memory is REQUIRED to pick up that data and
  82       guarantee its delivery.  no back-acknowledgement is required.
  83
  84       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  85     """
  86
  87     def __init__(self, name=None, regwid=64, addrwid=48):
  88
  89         self._regwid = regwid
  90         self._addrwid = addrwid
  91
  92         RecordObject.__init__(self, name=name)
  93
  94         # distinguish op type (ld/st)
  95         self.is_ld_i = Signal(reset_less=True)
  96         self.is_st_i = Signal(reset_less=True)
  97
  98         # LD/ST data length (TODO: other things may be needed)
  99         self.data_len = Signal(4, reset_less=True)
 100
 101         # common signals
 102         self.busy_o = Signal(reset_less=True)     # do not use if busy
 103         self.go_die_i = Signal(reset_less=True)   # back to reset
 104         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 105         # addr is valid (TLB, L1 etc.)
 106         self.addr_ok_o = Signal(reset_less=True)
 107         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 108
 109         # LD/ST
 110         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 111         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 112
 113     def connect_port(self, inport):
 114         print("connect_port", self, inport)
 115         return [self.is_ld_i.eq(inport.is_ld_i),
 116                 self.is_st_i.eq(inport.is_st_i),
 117                 self.data_len.eq(inport.data_len),
 118                 self.go_die_i.eq(inport.go_die_i),
 119                 self.addr.data.eq(inport.addr.data),
 120                 self.addr.ok.eq(inport.addr.ok),
 121                 self.st.eq(inport.st),
 122                 inport.ld.eq(self.ld),
 123                 inport.busy_o.eq(self.busy_o),
 124                 inport.addr_ok_o.eq(self.addr_ok_o),
 125                 inport.addr_exc_o.eq(self.addr_exc_o),
 126                 ]
 127
 128
 129 class PortInterfaceBase(Elaboratable):
 130     """PortInterfaceBase
 131
 132     Base class for PortInterface-compliant Memory read/writers
 133     """
 134
 135     def __init__(self, regwid=64, addrwid=4):
 136         self.regwid = regwid
 137         self.addrwid = addrwid
 138         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 139
 140     @property
 141     def addrbits(self):
 142         return log2_int(self.regwid//8)
 143
 144     def splitaddr(self, addr):
 145         """split the address into top and bottom bits of the memory granularity
 146         """
 147         return addr[:self.addrbits], addr[self.addrbits:]
 148
 149     def connect_port(self, inport):
 150         return self.pi.connect_port(inport)
 151
 152     def set_wr_addr(self, m, addr, mask): pass
 153     def set_rd_addr(self, m, addr, mask): pass
 154     def set_wr_data(self, m, data, wen): pass
 155     def get_rd_data(self, m): pass
 156
 157     def elaborate(self, platform):
 158         m = Module()
 159         comb, sync = m.d.comb, m.d.sync
 160
 161         # state-machine latches
 162         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 163         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 164         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 165         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 166         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 167         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 168         comb += cyc_l.s.eq(0)
 169         comb += cyc_l.r.eq(0)
 170         sync += adrok_l.s.eq(0)
 171         comb += adrok_l.r.eq(0)
 172
 173         # expand ld/st binary length/addr[:3] into unary bitmap
 174         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 175
 176         lds = Signal(reset_less=True)
 177         sts = Signal(reset_less=True)
 178         pi = self.pi
 179         comb += lds.eq(pi.is_ld_i & pi.busy_o)  # ld-req signals
 180         comb += sts.eq(pi.is_st_i & pi.busy_o)  # st-req signals
 181
 182         # activate mode
 183         with m.If(lds):
 184             comb += ld_active.s.eq(1)  # activate LD mode
 185         with m.Elif(sts):
 186             comb += st_active.s.eq(1)  # activate ST mode
 187
 188         # if now in "LD" mode: wait for addr_ok, then send the address out
 189         # to memory, acknowledge address, and send out LD data
 190         with m.If(ld_active.q):
 191             # set up LenExpander with the LD len and lower bits of addr
 192             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 193             comb += lenexp.len_i.eq(pi.data_len)
 194             comb += lenexp.addr_i.eq(lsbaddr)
 195             with m.If(pi.addr.ok & adrok_l.qn):
 196                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
 197                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 198                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 199
 200         # if now in "ST" mode: likewise do the same but with "ST"
 201         # to memory, acknowledge address, and send out LD data
 202         with m.If(st_active.q):
 203             # set up LenExpander with the ST len and lower bits of addr
 204             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 205             comb += lenexp.len_i.eq(pi.data_len)
 206             comb += lenexp.addr_i.eq(lsbaddr)
 207             with m.If(pi.addr.ok):
 208                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
 209                 with m.If(adrok_l.qn):
 210                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 211                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 212
 213         # for LD mode, when addr has been "ok'd", assume that (because this
 214         # is a "Memory" test-class) the memory read data is valid.
 215         comb += reset_l.s.eq(0)
 216         comb += reset_l.r.eq(0)
 217         lddata = Signal(self.regwid, reset_less=True)
 218         data, ldok = self.get_rd_data(m)
 219         comb += lddata.eq((data & lenexp.rexp_o) >>
 220                           (lenexp.addr_i*8))
 221         with m.If(ld_active.q & adrok_l.q):
 222             # shift data down before pushing out.  requires masking
 223             # from the *byte*-expanded version of LenExpand output
 224             comb += pi.ld.data.eq(lddata)  # put data out
 225             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 226             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 227
 228         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 229         with m.If(st_active.q & pi.st.ok):
 230             # shift data up before storing.  lenexp *bit* version of mask is
 231             # passed straight through as byte-level "write-enable" lines.
 232             stdata = Signal(self.regwid, reset_less=True)
 233             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 234             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 235             # and also handle the ready/stall/busy protocol
 236             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 237             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 238
 239         # ugly hack, due to simultaneous addr req-go acknowledge
 240         reset_delay = Signal(reset_less=True)
 241         sync += reset_delay.eq(reset_l.q)
 242         with m.If(reset_delay):
 243             comb += adrok_l.r.eq(1)     # address reset
 244
 245         # after waiting one cycle (reset_l is "sync" mode), reset the port
 246         with m.If(reset_l.q):
 247             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 248             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 249             comb += reset_l.r.eq(1)     # clear reset
 250             comb += adrok_l.r.eq(1)     # address reset
 251
 252         # LD/ST requested activates "busy"
 253         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 254             comb += busy_l.s.eq(1)
 255
 256         # monitor for an exception or the completion of LD.
 257         with m.If(self.pi.addr_exc_o):
 258             comb += busy_l.r.eq(1)
 259
 260         # however ST needs one cycle before busy is reset
 261         with m.If(self.pi.st.ok | self.pi.ld.ok):
 262             comb += cyc_l.s.eq(1)
 263
 264         with m.If(cyc_l.q):
 265             comb += cyc_l.r.eq(1)
 266             comb += busy_l.r.eq(1)
 267
 268         # busy latch outputs to interface
 269         comb += self.pi.busy_o.eq(busy_l.q)
 270
 271         return m
 272
 273     def ports(self):
 274         yield from self.pi.ports()
 275
 276
 277 class TestMemoryPortInterface(PortInterfaceBase):
 278     """TestMemoryPortInterface
 279
 280     This is a test class for simple verification of the LDSTCompUnit
 281     and for the simple core, to be able to run unit tests rapidly and
 282     with less other code in the way.
 283
 284     Versions of this which are *compatible* (conform with PortInterface)
 285     will include augmented-Wishbone Bus versions, including ones that
 286     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 287     possible version that complies with PortInterface".
 288     """
 289
 290     def __init__(self, regwid=64, addrwid=4):
 291         super().__init__(regwid, addrwid)
 292         # hard-code memory addressing width to 6 bits
 293         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 294
 295     def set_wr_addr(self, m, addr, mask):
 296         lsbaddr, msbaddr = self.splitaddr(addr)
 297         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 298
 299     def set_rd_addr(self, m, addr, mask):
 300         lsbaddr, msbaddr = self.splitaddr(addr)
 301         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 302
 303     def set_wr_data(self, m, data, wen):
 304         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 305         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 306         return Const(1, 1)
 307
 308     def get_rd_data(self, m):
 309         return self.mem.rdport.data, Const(1, 1)
 310
 311     def elaborate(self, platform):
 312         m = super().elaborate(platform)
 313
 314         # add TestMemory as submodule
 315         m.submodules.mem = self.mem
 316
 317         return m
 318
 319     def ports(self):
 320         yield from super().ports()
 321         # TODO: memory ports