src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34 from nmutil.util import Display
  35
  36 import unittest
  37
  38
  39 class PortInterface(RecordObject):
  40     """PortInterface
  41
  42     defines the interface - the API - that the LDSTCompUnit connects
  43     to.  note that this is NOT a "fire-and-forget" interface.  the
  44     LDSTCompUnit *must* be kept appraised that the request is in
  45     progress, and only when it has a 100% successful completion
  46     can the notification be given (busy dropped).
  47
  48     The interface FSM rules are as follows:
  49
  50     * if busy_o is asserted, a LD/ST is in progress.  further
  51       requests may not be made until busy_o is deasserted.
  52
  53     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  54       will immediately be asserted and remain asserted.
  55
  56     * addr.ok is to be asserted when the LD/ST address is known.
  57       addr.data is to be valid on the same cycle.
  58
  59       addr.ok and addr.data must REMAIN asserted until busy_o
  60       is de-asserted.  this ensures that there is no need
  61       for the L0 Cache/Buffer to have an additional address latch
  62       (because the LDSTCompUnit already has it)
  63
  64     * addr_ok_o (or exception.happened) must be waited for.  these will
  65       be asserted *only* for one cycle and one cycle only.
  66
  67     * exception.happened will be asserted if there is no chance that the
  68       memory request may be fulfilled.
  69
  70       busy_o is deasserted on the same cycle as exception.happened is asserted.
  71
  72     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  73       HUNDRED PERCENT guarantee that the memory request will be
  74       fulfilled.
  75
  76     * for a LD, ld.ok will be asserted - for only one clock cycle -
  77       at any point in the future that is acceptable to the underlying
  78       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  79
  80       busy_o is deasserted on the same cycle as ld.ok is asserted.
  81
  82     * for a ST, st.ok may be asserted only after addr_ok_o had been
  83       asserted, alongside valid st.data at the same time.  st.ok
  84       must only be asserted for one cycle.
  85
  86       the underlying Memory is REQUIRED to pick up that data and
  87       guarantee its delivery.  no back-acknowledgement is required.
  88
  89       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  90     """
  91
  92     def __init__(self, name=None, regwid=64, addrwid=48):
  93
  94         self._regwid = regwid
  95         self._addrwid = addrwid
  96
  97         RecordObject.__init__(self, name=name)
  98
  99         # distinguish op type (ld/st/dcbz)
 100         self.is_ld_i    = Signal(reset_less=True)
 101         self.is_st_i    = Signal(reset_less=True)
 102         self.is_dcbz_i  = Signal(reset_less=True)
 103         ## self.is_dcbz = self.is_dcbz_i # renamed signal hack
 104
 105         # LD/ST data length (TODO: other things may be needed)
 106         self.data_len = Signal(4, reset_less=True)
 107
 108         # common signals
 109         self.busy_o = Signal(reset_less=True)     # do not use if busy
 110         self.go_die_i = Signal(reset_less=True)   # back to reset
 111         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 112         # addr is valid (TLB, L1 etc.)
 113         self.addr_ok_o = Signal(reset_less=True)
 114         self.exc_o = LDSTException("exc")
 115
 116         # LD/ST
 117         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 118         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 119
 120         # additional "modes"
 121         self.is_nc         = Signal()  # no cacheing
 122         self.msr_pr        = Signal()  # 1==virtual, 0==privileged
 123
 124         # mmu
 125         self.mmu_done          = Signal() # keep for now
 126
 127         # dcache
 128         self.ldst_error        = Signal()
 129         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 130         self.cache_paradox     = Signal()
 131
 132     def connect_port(self, inport):
 133         print("connect_port", self, inport)
 134         return [self.is_ld_i.eq(inport.is_ld_i),
 135                 self.is_st_i.eq(inport.is_st_i),
 136                 self.is_nc.eq(inport.is_nc),
 137                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 138                 self.data_len.eq(inport.data_len),
 139                 self.go_die_i.eq(inport.go_die_i),
 140                 self.addr.data.eq(inport.addr.data),
 141                 self.addr.ok.eq(inport.addr.ok),
 142                 self.st.eq(inport.st),
 143                 self.msr_pr.eq(inport.msr_pr),
 144                 inport.ld.eq(self.ld),
 145                 inport.busy_o.eq(self.busy_o),
 146                 inport.addr_ok_o.eq(self.addr_ok_o),
 147                 inport.exc_o.eq(self.exc_o),
 148                 inport.mmu_done.eq(self.mmu_done),
 149                 inport.ldst_error.eq(self.ldst_error),
 150                 inport.cache_paradox.eq(self.cache_paradox)
 151                 ]
 152
 153
 154 class PortInterfaceBase(Elaboratable):
 155     """PortInterfaceBase
 156
 157     Base class for PortInterface-compliant Memory read/writers
 158     """
 159
 160     def __init__(self, regwid=64, addrwid=4):
 161         self.regwid = regwid
 162         self.addrwid = addrwid
 163         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 164
 165     @property
 166     def addrbits(self):
 167         return log2_int(self.regwid//8)
 168
 169     def splitaddr(self, addr):
 170         """split the address into top and bottom bits of the memory granularity
 171         """
 172         return addr[:self.addrbits], addr[self.addrbits:]
 173
 174     def connect_port(self, inport):
 175         return self.pi.connect_port(inport)
 176
 177     def set_wr_addr(self, m, addr, mask, misalign, msr_pr): pass
 178     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 179     def set_wr_data(self, m, data, wen): pass
 180     def get_rd_data(self, m): pass
 181     def set_dcbz_addr(self, m, addr): pass
 182
 183     def elaborate(self, platform):
 184         m = Module()
 185         comb, sync = m.d.comb, m.d.sync
 186
 187         # state-machine latches
 188         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 189         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 190         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 191         dcbz_active = SRLatch(False, name="dcbz_active")
 192         m.submodules.dcbz_active = dcbz_active # this one is new and untested
 193         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 194         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 195         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 196         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 197
 198         self.busy_l = busy_l
 199
 200         comb += Display("PortInterfaceBase dcbz_active.q=%i",dcbz_active.q)
 201
 202         sync += st_done.s.eq(0)
 203         comb += st_done.r.eq(0)
 204         comb += st_active.r.eq(0)
 205         comb += ld_active.r.eq(0)
 206         comb += dcbz_active.r.eq(0)
 207         comb += cyc_l.s.eq(0)
 208         comb += cyc_l.r.eq(0)
 209         comb += busy_l.s.eq(0)
 210         comb += busy_l.r.eq(0)
 211         sync += adrok_l.s.eq(0)
 212         comb += adrok_l.r.eq(0)
 213
 214         # expand ld/st binary length/addr[:3] into unary bitmap
 215         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 216
 217         lds = Signal(reset_less=True)
 218         sts = Signal(reset_less=True)
 219         dcbzs = Signal(reset_less=True)
 220         pi = self.pi
 221         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 222         comb += sts.eq(pi.is_st_i)  # st-req signals
 223         comb += dcbzs.eq(pi.is_dcbz_i)  # dcbz-req signals (new, untested)
 224         pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv
 225
 226         # detect busy "edge"
 227         busy_delay = Signal()
 228         busy_edge = Signal()
 229         sync += busy_delay.eq(pi.busy_o)
 230         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 231
 232         # misalignment detection: bits at end of lenexpand are set.
 233         # when using the L0CacheBuffer "data expander" which splits requests
 234         # into *two* PortInterfaces, this acts as a "safety check".
 235         misalign = Signal()
 236         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 237
 238
 239         # activate mode: only on "edge"
 240         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 241         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 242         comb += dcbz_active.s.eq(rising_edge(m, dcbzs))  # activate ST mode
 243
 244         # LD/ST requested activates "busy" (only if not already busy)
 245         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 246             comb += busy_l.s.eq(~busy_delay)
 247
 248         # if now in "LD" mode: wait for addr_ok, then send the address out
 249         # to memory, acknowledge address, and send out LD data
 250         with m.If(ld_active.q):
 251             # set up LenExpander with the LD len and lower bits of addr
 252             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 253             comb += lenexp.len_i.eq(pi.data_len)
 254             comb += lenexp.addr_i.eq(lsbaddr)
 255             with m.If(pi.addr.ok & adrok_l.qn):
 256                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 257                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 258                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 259
 260         # if now in "DCBZ" mode: wait for addr_ok, then send the address out
 261         # to memory, acknowledge address, and send out LD data
 262         with m.If(dcbz_active.q):
 263             self.set_dcbz_addr(m, pi.addr.data)
 264
 265         # if now in "ST" mode: likewise do the same but with "ST"
 266         # to memory, acknowledge address, and send out LD data
 267         with m.If(st_active.q):
 268             # set up LenExpander with the ST len and lower bits of addr
 269             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 270             comb += lenexp.len_i.eq(pi.data_len)
 271             comb += lenexp.addr_i.eq(lsbaddr)
 272             with m.If(pi.addr.ok):
 273                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 274                 with m.If(adrok_l.qn):
 275                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 276                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 277
 278         # for LD mode, when addr has been "ok'd", assume that (because this
 279         # is a "Memory" test-class) the memory read data is valid.
 280         comb += reset_l.s.eq(0)
 281         comb += reset_l.r.eq(0)
 282         lddata = Signal(self.regwid, reset_less=True)
 283         data, ldok = self.get_rd_data(m)
 284         comb += lddata.eq((data & lenexp.rexp_o) >>
 285                           (lenexp.addr_i*8))
 286         with m.If(ld_active.q & adrok_l.q):
 287             # shift data down before pushing out.  requires masking
 288             # from the *byte*-expanded version of LenExpand output
 289             comb += pi.ld.data.eq(lddata)  # put data out
 290             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 291             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 292
 293         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 294         with m.If(st_active.q & pi.st.ok):
 295             # shift data up before storing.  lenexp *bit* version of mask is
 296             # passed straight through as byte-level "write-enable" lines.
 297             stdata = Signal(self.regwid, reset_less=True)
 298             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 299             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 300             # and also handle the ready/stall/busy protocol
 301             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 302             sync += st_done.s.eq(1)     # store done trigger
 303         with m.If(st_done.q):
 304             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 305
 306         # ugly hack, due to simultaneous addr req-go acknowledge
 307         reset_delay = Signal(reset_less=True)
 308         sync += reset_delay.eq(reset_l.q)
 309         with m.If(reset_delay):
 310             comb += adrok_l.r.eq(1)     # address reset
 311
 312         # after waiting one cycle (reset_l is "sync" mode), reset the port
 313         with m.If(reset_l.q):
 314             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 315             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 316             comb += dcbz_active.r.eq(1)   # leave the DCBZ active for 1 cycle
 317             comb += reset_l.r.eq(1)     # clear reset
 318             comb += adrok_l.r.eq(1)     # address reset
 319             comb += st_done.r.eq(1)     # store done reset
 320
 321         # monitor for an exception, clear busy immediately
 322         with m.If(self.pi.exc_o.happened):
 323             comb += busy_l.r.eq(1)
 324
 325         # however ST needs one cycle before busy is reset
 326         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 327         with m.If(reset_l.s):
 328             comb += cyc_l.s.eq(1)
 329
 330         with m.If(cyc_l.q):
 331             comb += cyc_l.r.eq(1)
 332             comb += busy_l.r.eq(1)
 333
 334         # busy latch outputs to interface
 335         comb += pi.busy_o.eq(busy_l.q)
 336
 337         return m
 338
 339     def ports(self):
 340         yield from self.pi.ports()
 341
 342
 343 class TestMemoryPortInterface(PortInterfaceBase):
 344     """TestMemoryPortInterface
 345
 346     This is a test class for simple verification of the LDSTCompUnit
 347     and for the simple core, to be able to run unit tests rapidly and
 348     with less other code in the way.
 349
 350     Versions of this which are *compatible* (conform with PortInterface)
 351     will include augmented-Wishbone Bus versions, including ones that
 352     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 353     possible version that complies with PortInterface".
 354     """
 355
 356     def __init__(self, regwid=64, addrwid=4):
 357         super().__init__(regwid, addrwid)
 358         # hard-code memory addressing width to 6 bits
 359         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 360
 361     def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
 362         lsbaddr, msbaddr = self.splitaddr(addr)
 363         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 364
 365     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 366         lsbaddr, msbaddr = self.splitaddr(addr)
 367         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 368
 369     def set_wr_data(self, m, data, wen):
 370         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 371         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 372         return Const(1, 1)
 373
 374     def get_rd_data(self, m):
 375         return self.mem.rdport.data, Const(1, 1)
 376
 377     def elaborate(self, platform):
 378         m = super().elaborate(platform)
 379
 380         # add TestMemory as submodule
 381         m.submodules.mem = self.mem
 382
 383         return m
 384
 385     def ports(self):
 386         yield from super().ports()
 387         # TODO: memory ports