src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import verilog, rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23 from nmigen.hdl.rec import Record, Layout
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.decoder.power_enums import InternalOp
  28 from soc.regfile.regfile import ortreereduce
  29 from nmutil.util import treereduce
  30
  31 from soc.decoder.power_decoder2 import Data
  32 #from nmutil.picker import PriorityPicker
  33 from nmigen.lib.coding import PriorityEncoder
  34 from soc.scoreboard.addr_split import LDSTSplitter
  35 from soc.scoreboard.addr_match import LenExpand
  36
  37 # for testing purposes
  38 from soc.experiment.testmem import TestMemory # TODO: replace with TMLSUI
  39 # TODO: from soc.experiment.testmem import TestMemoryLoadStoreUnit
  40
  41 import unittest
  42
  43
  44 class PortInterface(RecordObject):
  45     """PortInterface
  46
  47     defines the interface - the API - that the LDSTCompUnit connects
  48     to.  note that this is NOT a "fire-and-forget" interface.  the
  49     LDSTCompUnit *must* be kept appraised that the request is in
  50     progress, and only when it has a 100% successful completion
  51     can the notification be given (busy dropped).
  52
  53     The interface FSM rules are as follows:
  54
  55     * if busy_o is asserted, a LD/ST is in progress.  further
  56       requests may not be made until busy_o is deasserted.
  57
  58     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  59       will immediately be asserted and remain asserted.
  60
  61     * addr.ok is to be asserted when the LD/ST address is known.
  62       addr.data is to be valid on the same cycle.
  63
  64       addr.ok and addr.data must REMAIN asserted until busy_o
  65       is de-asserted.  this ensures that there is no need
  66       for the L0 Cache/Buffer to have an additional address latch
  67       (because the LDSTCompUnit already has it)
  68
  69     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  70       be asserted *only* for one cycle and one cycle only.
  71
  72     * addr_exc_o will be asserted if there is no chance that the
  73       memory request may be fulfilled.
  74
  75       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  76
  77     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  78       HUNDRED PERCENT guarantee that the memory request will be
  79       fulfilled.
  80
  81     * for a LD, ld.ok will be asserted - for only one clock cycle -
  82       at any point in the future that is acceptable to the underlying
  83       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  84
  85       busy_o is deasserted on the same cycle as ld.ok is asserted.
  86
  87     * for a ST, st.ok may be asserted only after addr_ok_o had been
  88       asserted, alongside valid st.data at the same time.  st.ok
  89       must only be asserted for one cycle.
  90
  91       the underlying Memory is REQUIRED to pick up that data and
  92       guarantee its delivery.  no back-acknowledgement is required.
  93
  94       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  95     """
  96
  97     def __init__(self, name=None, regwid=64, addrwid=48):
  98
  99         self._regwid = regwid
 100         self._addrwid = addrwid
 101
 102         RecordObject.__init__(self, name=name)
 103
 104         # distinguish op type (ld/st)
 105         self.is_ld_i = Signal(reset_less=True)
 106         self.is_st_i = Signal(reset_less=True)
 107
 108         # LD/ST data length (TODO: other things may be needed)
 109         self.data_len = Signal(4, reset_less=True)
 110
 111         # common signals
 112         self.busy_o = Signal(reset_less=True)     # do not use if busy
 113         self.go_die_i = Signal(reset_less=True)   # back to reset
 114         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 115         # addr is valid (TLB, L1 etc.)
 116         self.addr_ok_o = Signal(reset_less=True)
 117         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 118
 119         # LD/ST
 120         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 121         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 122
 123     def connect_port(self, inport):
 124         print ("connect_port", self, inport)
 125         return [self.is_ld_i.eq(inport.is_ld_i),
 126                 self.is_st_i.eq(inport.is_st_i),
 127                 self.data_len.eq(inport.data_len),
 128                 self.go_die_i.eq(inport.go_die_i),
 129                 self.addr.data.eq(inport.addr.data),
 130                 self.addr.ok.eq(inport.addr.ok),
 131                 self.st.eq(inport.st),
 132                 inport.ld.eq(self.ld),
 133                 inport.busy_o.eq(self.busy_o),
 134                 inport.addr_ok_o.eq(self.addr_ok_o),
 135                 inport.addr_exc_o.eq(self.addr_exc_o),
 136                 ]
 137
 138
 139 class LDSTPort(Elaboratable):
 140     def __init__(self, idx, regwid=64, addrwid=48):
 141         self.pi = PortInterface("ldst_port%d" % idx, regwid, addrwid)
 142
 143     def elaborate(self, platform):
 144         m = Module()
 145         comb, sync = m.d.comb, m.d.sync
 146
 147         # latches
 148         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 149         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 150         comb += cyc_l.s.eq(0)
 151         comb += cyc_l.r.eq(0)
 152
 153         # this is a little weird: we let the L0Cache/Buffer set
 154         # the outputs: this module just monitors "state".
 155
 156         # LD/ST requested activates "busy"
 157         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 158             comb += busy_l.s.eq(1)
 159
 160         # monitor for an exception or the completion of LD.
 161         with m.If(self.pi.addr_exc_o):
 162             comb += busy_l.r.eq(1)
 163
 164         # however ST needs one cycle before busy is reset
 165         with m.If(self.pi.st.ok | self.pi.ld.ok):
 166             comb += cyc_l.s.eq(1)
 167
 168         with m.If(cyc_l.q):
 169             comb += cyc_l.r.eq(1)
 170             comb += busy_l.r.eq(1)
 171
 172         # busy latch outputs to interface
 173         comb += self.pi.busy_o.eq(busy_l.q)
 174
 175         return m
 176
 177     def connect_port(self, inport):
 178         print ("connect_port", self.pi, inport)
 179         return self.pi.connect_port(inport)
 180
 181     def __iter__(self):
 182         yield self.pi.is_ld_i
 183         yield self.pi.is_st_i
 184         yield from self.pi.data_len
 185         yield self.pi.busy_o
 186         yield self.pi.go_die_i
 187         yield from self.pi.addr.ports()
 188         yield self.pi.addr_ok_o
 189         yield self.pi.addr_exc_o
 190
 191         yield from self.pi.ld.ports()
 192         yield from self.pi.st.ports()
 193
 194     def ports(self):
 195         return list(self)
 196
 197
 198 class TestMemoryPortInterface(Elaboratable):
 199     """TestMemoryPortInterface
 200
 201     This is a test class for simple verification of the LDSTCompUnit
 202     and for the simple core, to be able to run unit tests rapidly and
 203     with less other code in the way.
 204
 205     Versions of this which are *compatible* (conform with PortInterface)
 206     will include augmented-Wishbone Bus versions, including ones that
 207     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 208     possible version that complies with PortInterface".
 209     """
 210
 211     def __init__(self, regwid=64, addrwid=4):
 212         # hard-code memory addressing width to 6 bits
 213         self.mem = TestMemory(regwid, 5, granularity=regwid//8,
 214                               init=False)
 215         self.regwid = regwid
 216         self.addrwid = addrwid
 217         self.lpi = LDSTPort(0, regwid, addrwid)
 218         self.pi = self.lpi.pi
 219
 220     @property
 221     def addrbits(self):
 222         return log2_int(self.mem.regwid//8)
 223
 224     def splitaddr(self, addr):
 225         """split the address into top and bottom bits of the memory granularity
 226         """
 227         return addr[:self.addrbits], addr[self.addrbits:]
 228
 229     def connect_port(self, inport):
 230         return self.lpi.connect_port(inport)
 231
 232     def elaborate(self, platform):
 233         m = Module()
 234         comb, sync = m.d.comb, m.d.sync
 235
 236         # add TestMemory as submodule
 237         m.submodules.mem = self.mem
 238
 239         # connect the ports as modules
 240         m.submodules.port0 = self.lpi
 241
 242         # state-machine latches
 243         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 244         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 245         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 246         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 247
 248         # expand ld/st binary length/addr[:3] into unary bitmap
 249         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 250
 251         lds = Signal(reset_less=True)
 252         sts = Signal(reset_less=True)
 253         pi = self.pi
 254         comb += lds.eq(pi.is_ld_i & pi.busy_o)  # ld-req signals
 255         comb += sts.eq(pi.is_st_i & pi.busy_o)  # st-req signals
 256
 257         # convenience variables to reference the "picked" port
 258         ldport = pi
 259         stport = pi
 260         # and the memory ports
 261         rdport = self.mem.rdport
 262         wrport = self.mem.wrport
 263
 264         # Priority-Pickers pick one and only one request, capture its index.
 265         # from that point on this code *only* "listens" to that port.
 266
 267         sync += adrok_l.s.eq(0)
 268         comb += adrok_l.r.eq(0)
 269         with m.If(lds):
 270             comb += ld_active.s.eq(1)  # activate LD mode
 271         with m.Elif(sts):
 272             comb += st_active.s.eq(1)  # activate ST mode
 273
 274         # from this point onwards, with the port "picked", it stays picked
 275         # until ld_active (or st_active) are de-asserted.
 276
 277         # if now in "LD" mode: wait for addr_ok, then send the address out
 278         # to memory, acknowledge address, and send out LD data
 279         with m.If(ld_active.q):
 280             # set up LenExpander with the LD len and lower bits of addr
 281             lsbaddr, msbaddr = self.splitaddr(ldport.addr.data)
 282             comb += lenexp.len_i.eq(ldport.data_len)
 283             comb += lenexp.addr_i.eq(lsbaddr)
 284             with m.If(ldport.addr.ok & adrok_l.qn):
 285                 comb += rdport.addr.eq(msbaddr) # addr ok, send thru
 286                 comb += ldport.addr_ok_o.eq(1)  # acknowledge addr ok
 287                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 288
 289         # if now in "ST" mode: likewise do the same but with "ST"
 290         # to memory, acknowledge address, and send out LD data
 291         with m.If(st_active.q):
 292             # set up LenExpander with the ST len and lower bits of addr
 293             lsbaddr, msbaddr = self.splitaddr(stport.addr.data)
 294             comb += lenexp.len_i.eq(stport.data_len)
 295             comb += lenexp.addr_i.eq(lsbaddr)
 296             with m.If(stport.addr.ok):
 297                 comb += wrport.addr.eq(msbaddr)  # addr ok, send thru
 298                 with m.If(adrok_l.qn):
 299                     comb += stport.addr_ok_o.eq(1)  # acknowledge addr ok
 300                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 301
 302         # NOTE: in both these, below, the port itself takes care
 303         # of de-asserting its "busy_o" signal, based on either ld.ok going
 304         # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
 305
 306         # for LD mode, when addr has been "ok'd", assume that (because this
 307         # is a "Memory" test-class) the memory read data is valid.
 308         comb += reset_l.s.eq(0)
 309         comb += reset_l.r.eq(0)
 310         with m.If(ld_active.q & adrok_l.q):
 311             # shift data down before pushing out.  requires masking
 312             # from the *byte*-expanded version of LenExpand output
 313             lddata = Signal(self.regwid, reset_less=True)
 314             # TODO: replace rdport.data with LoadStoreUnitInterface.x_load_data
 315             # and also handle the ready/stall/busy protocol
 316             comb += lddata.eq((rdport.data & lenexp.rexp_o) >>
 317                               (lenexp.addr_i*8))
 318             comb += ldport.ld.data.eq(lddata)  # put data out
 319             comb += ldport.ld.ok.eq(1)           # indicate data valid
 320             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 321
 322         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 323         with m.If(st_active.q & stport.st.ok):
 324             # shift data up before storing.  lenexp *bit* version of mask is
 325             # passed straight through as byte-level "write-enable" lines.
 326             stdata = Signal(self.regwid, reset_less=True)
 327             comb += stdata.eq(stport.st.data << (lenexp.addr_i*8))
 328             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 329             # and also handle the ready/stall/busy protocol
 330             comb += wrport.data.eq(stdata)  # write st to mem
 331             comb += wrport.en.eq(lenexp.lexp_o) # enable writes
 332             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 333
 334         # ugly hack, due to simultaneous addr req-go acknowledge
 335         reset_delay = Signal(reset_less=True)
 336         sync += reset_delay.eq(reset_l.q)
 337         with m.If(reset_delay):
 338             comb += adrok_l.r.eq(1)     # address reset
 339
 340         # after waiting one cycle (reset_l is "sync" mode), reset the port
 341         with m.If(reset_l.q):
 342             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 343             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 344             comb += reset_l.r.eq(1)     # clear reset
 345             comb += adrok_l.r.eq(1)     # address reset
 346
 347         return m
 348
 349     def ports(self):
 350         for p in self.dports:
 351             yield from p.ports()
 352
 353
 354