src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23
  24 from nmutil.latch import SRLatch, latchregister
  25 from nmutil.util import rising_edge
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.scoreboard.addr_match import LenExpand
  28
  29 # for testing purposes
  30 from soc.experiment.testmem import TestMemory
  31
  32 import unittest
  33
  34
  35 class PortInterface(RecordObject):
  36     """PortInterface
  37
  38     defines the interface - the API - that the LDSTCompUnit connects
  39     to.  note that this is NOT a "fire-and-forget" interface.  the
  40     LDSTCompUnit *must* be kept appraised that the request is in
  41     progress, and only when it has a 100% successful completion
  42     can the notification be given (busy dropped).
  43
  44     The interface FSM rules are as follows:
  45
  46     * if busy_o is asserted, a LD/ST is in progress.  further
  47       requests may not be made until busy_o is deasserted.
  48
  49     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  50       will immediately be asserted and remain asserted.
  51
  52     * addr.ok is to be asserted when the LD/ST address is known.
  53       addr.data is to be valid on the same cycle.
  54
  55       addr.ok and addr.data must REMAIN asserted until busy_o
  56       is de-asserted.  this ensures that there is no need
  57       for the L0 Cache/Buffer to have an additional address latch
  58       (because the LDSTCompUnit already has it)
  59
  60     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  61       be asserted *only* for one cycle and one cycle only.
  62
  63     * addr_exc_o will be asserted if there is no chance that the
  64       memory request may be fulfilled.
  65
  66       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  67
  68     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  69       HUNDRED PERCENT guarantee that the memory request will be
  70       fulfilled.
  71
  72     * for a LD, ld.ok will be asserted - for only one clock cycle -
  73       at any point in the future that is acceptable to the underlying
  74       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  75
  76       busy_o is deasserted on the same cycle as ld.ok is asserted.
  77
  78     * for a ST, st.ok may be asserted only after addr_ok_o had been
  79       asserted, alongside valid st.data at the same time.  st.ok
  80       must only be asserted for one cycle.
  81
  82       the underlying Memory is REQUIRED to pick up that data and
  83       guarantee its delivery.  no back-acknowledgement is required.
  84
  85       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  86     """
  87
  88     def __init__(self, name=None, regwid=64, addrwid=48):
  89
  90         self._regwid = regwid
  91         self._addrwid = addrwid
  92
  93         RecordObject.__init__(self, name=name)
  94
  95         # distinguish op type (ld/st)
  96         self.is_ld_i = Signal(reset_less=True)
  97         self.is_st_i = Signal(reset_less=True)
  98
  99         # LD/ST data length (TODO: other things may be needed)
 100         self.data_len = Signal(4, reset_less=True)
 101
 102         # common signals
 103         self.busy_o = Signal(reset_less=True)     # do not use if busy
 104         self.go_die_i = Signal(reset_less=True)   # back to reset
 105         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 106         # addr is valid (TLB, L1 etc.)
 107         self.addr_ok_o = Signal(reset_less=True)
 108         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 109
 110         # LD/ST
 111         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 112         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 113
 114     def connect_port(self, inport):
 115         print("connect_port", self, inport)
 116         return [self.is_ld_i.eq(inport.is_ld_i),
 117                 self.is_st_i.eq(inport.is_st_i),
 118                 self.data_len.eq(inport.data_len),
 119                 self.go_die_i.eq(inport.go_die_i),
 120                 self.addr.data.eq(inport.addr.data),
 121                 self.addr.ok.eq(inport.addr.ok),
 122                 self.st.eq(inport.st),
 123                 inport.ld.eq(self.ld),
 124                 inport.busy_o.eq(self.busy_o),
 125                 inport.addr_ok_o.eq(self.addr_ok_o),
 126                 inport.addr_exc_o.eq(self.addr_exc_o),
 127                 ]
 128
 129
 130 class PortInterfaceBase(Elaboratable):
 131     """PortInterfaceBase
 132
 133     Base class for PortInterface-compliant Memory read/writers
 134     """
 135
 136     def __init__(self, regwid=64, addrwid=4):
 137         self.regwid = regwid
 138         self.addrwid = addrwid
 139         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 140
 141     @property
 142     def addrbits(self):
 143         return log2_int(self.regwid//8)
 144
 145     def splitaddr(self, addr):
 146         """split the address into top and bottom bits of the memory granularity
 147         """
 148         return addr[:self.addrbits], addr[self.addrbits:]
 149
 150     def connect_port(self, inport):
 151         return self.pi.connect_port(inport)
 152
 153     def set_wr_addr(self, m, addr, mask): pass
 154     def set_rd_addr(self, m, addr, mask): pass
 155     def set_wr_data(self, m, data, wen): pass
 156     def get_rd_data(self, m): pass
 157
 158     def elaborate(self, platform):
 159         m = Module()
 160         comb, sync = m.d.comb, m.d.sync
 161
 162         # state-machine latches
 163         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 164         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 165         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 166         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 167         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 168         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 169         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 170
 171         self.busy_l = busy_l
 172
 173         sync += st_done.s.eq(0)
 174         comb += st_done.r.eq(0)
 175         comb += st_active.r.eq(0)
 176         comb += ld_active.r.eq(0)
 177         comb += cyc_l.s.eq(0)
 178         comb += cyc_l.r.eq(0)
 179         comb += busy_l.s.eq(0)
 180         comb += busy_l.r.eq(0)
 181         sync += adrok_l.s.eq(0)
 182         comb += adrok_l.r.eq(0)
 183
 184         # expand ld/st binary length/addr[:3] into unary bitmap
 185         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 186
 187         lds = Signal(reset_less=True)
 188         sts = Signal(reset_less=True)
 189         pi = self.pi
 190         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 191         comb += sts.eq(pi.is_st_i)  # st-req signals
 192
 193         # detect busy "edge"
 194         busy_delay = Signal()
 195         busy_edge = Signal()
 196         sync += busy_delay.eq(pi.busy_o)
 197         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 198
 199         # activate mode: only on "edge"
 200         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 201         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 202
 203         # LD/ST requested activates "busy" (only if not already busy)
 204         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 205             comb += busy_l.s.eq(~busy_delay)
 206
 207         # if now in "LD" mode: wait for addr_ok, then send the address out
 208         # to memory, acknowledge address, and send out LD data
 209         with m.If(ld_active.q):
 210             # set up LenExpander with the LD len and lower bits of addr
 211             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 212             comb += lenexp.len_i.eq(pi.data_len)
 213             comb += lenexp.addr_i.eq(lsbaddr)
 214             with m.If(pi.addr.ok & adrok_l.qn):
 215                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
 216                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 217                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 218
 219         # if now in "ST" mode: likewise do the same but with "ST"
 220         # to memory, acknowledge address, and send out LD data
 221         with m.If(st_active.q):
 222             # set up LenExpander with the ST len and lower bits of addr
 223             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 224             comb += lenexp.len_i.eq(pi.data_len)
 225             comb += lenexp.addr_i.eq(lsbaddr)
 226             with m.If(pi.addr.ok):
 227                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
 228                 with m.If(adrok_l.qn):
 229                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 230                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 231
 232         # for LD mode, when addr has been "ok'd", assume that (because this
 233         # is a "Memory" test-class) the memory read data is valid.
 234         comb += reset_l.s.eq(0)
 235         comb += reset_l.r.eq(0)
 236         lddata = Signal(self.regwid, reset_less=True)
 237         data, ldok = self.get_rd_data(m)
 238         comb += lddata.eq((data & lenexp.rexp_o) >>
 239                           (lenexp.addr_i*8))
 240         with m.If(ld_active.q & adrok_l.q):
 241             # shift data down before pushing out.  requires masking
 242             # from the *byte*-expanded version of LenExpand output
 243             comb += pi.ld.data.eq(lddata)  # put data out
 244             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 245             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 246
 247         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 248         with m.If(st_active.q & pi.st.ok):
 249             # shift data up before storing.  lenexp *bit* version of mask is
 250             # passed straight through as byte-level "write-enable" lines.
 251             stdata = Signal(self.regwid, reset_less=True)
 252             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 253             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 254             # and also handle the ready/stall/busy protocol
 255             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 256             sync += st_done.s.eq(1)     # store done trigger
 257         with m.If(st_done.q):
 258             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 259
 260         # ugly hack, due to simultaneous addr req-go acknowledge
 261         reset_delay = Signal(reset_less=True)
 262         sync += reset_delay.eq(reset_l.q)
 263         with m.If(reset_delay):
 264             comb += adrok_l.r.eq(1)     # address reset
 265
 266         # after waiting one cycle (reset_l is "sync" mode), reset the port
 267         with m.If(reset_l.q):
 268             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 269             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 270             comb += reset_l.r.eq(1)     # clear reset
 271             comb += adrok_l.r.eq(1)     # address reset
 272             comb += st_done.r.eq(1)     # store done reset
 273
 274         # monitor for an exception or the completion of LD.
 275         with m.If(self.pi.addr_exc_o):
 276             comb += busy_l.r.eq(1)
 277
 278         # however ST needs one cycle before busy is reset
 279         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 280         with m.If(reset_l.s):
 281             comb += cyc_l.s.eq(1)
 282
 283         with m.If(cyc_l.q):
 284             comb += cyc_l.r.eq(1)
 285             comb += busy_l.r.eq(1)
 286
 287         # busy latch outputs to interface
 288         comb += pi.busy_o.eq(busy_l.q)
 289
 290         return m
 291
 292     def ports(self):
 293         yield from self.pi.ports()
 294
 295
 296 class TestMemoryPortInterface(PortInterfaceBase):
 297     """TestMemoryPortInterface
 298
 299     This is a test class for simple verification of the LDSTCompUnit
 300     and for the simple core, to be able to run unit tests rapidly and
 301     with less other code in the way.
 302
 303     Versions of this which are *compatible* (conform with PortInterface)
 304     will include augmented-Wishbone Bus versions, including ones that
 305     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 306     possible version that complies with PortInterface".
 307     """
 308
 309     def __init__(self, regwid=64, addrwid=4):
 310         super().__init__(regwid, addrwid)
 311         # hard-code memory addressing width to 6 bits
 312         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 313
 314     def set_wr_addr(self, m, addr, mask):
 315         lsbaddr, msbaddr = self.splitaddr(addr)
 316         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 317
 318     def set_rd_addr(self, m, addr, mask):
 319         lsbaddr, msbaddr = self.splitaddr(addr)
 320         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 321
 322     def set_wr_data(self, m, data, wen):
 323         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 324         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 325         return Const(1, 1)
 326
 327     def get_rd_data(self, m):
 328         return self.mem.rdport.data, Const(1, 1)
 329
 330     def elaborate(self, platform):
 331         m = super().elaborate(platform)
 332
 333         # add TestMemory as submodule
 334         m.submodules.mem = self.mem
 335
 336         return m
 337
 338     def ports(self):
 339         yield from super().ports()
 340         # TODO: memory ports
 341
 342 class TestCachedMemoryPortInterface(PortInterfaceBase):
 343     """TestCacheMemoryPortInterface
 344
 345     This is a test class for simple verification of LDSTSplitter
 346     conforming to PortInterface,
 347     """
 348
 349     def __init__(self, regwid=64, addrwid=4):
 350         super().__init__(regwid, addrwid)
 351         # hard-code memory addressing width to 6 bits
 352         self.mem = None
 353
 354     def set_wr_addr(self, m, addr, mask):
 355         lsbaddr, msbaddr = self.splitaddr(addr)
 356         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 357
 358     def set_rd_addr(self, m, addr, mask):
 359         lsbaddr, msbaddr = self.splitaddr(addr)
 360         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 361
 362     def set_wr_data(self, m, data, wen):
 363         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 364         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 365         return Const(1, 1)
 366
 367     def get_rd_data(self, m):
 368         return self.mem.rdport.data, Const(1, 1)
 369
 370     def elaborate(self, platform):
 371         m = super().elaborate(platform)
 372
 373         # add TestMemory as submodule
 374         m.submodules.mem = self.mem
 375
 376         return m
 377
 378     def ports(self):
 379         yield from super().ports()
 380         # TODO: memory ports