src/soc/experiment/sr/sr.py

   1 from nmigen import *
   2 from nmigen.back import rtlil
   3
   4
   5 sr_set = Signal(3)
   6 sr_clr = Signal(3)
   7 q = Signal(3)
   8
   9 m = Module()
  10 m.submodules += Instance("$sr",
  11     p_WIDTH=3,
  12     p_SET_POLARITY=1,
  13     p_CLR_POLARITY=1,
  14         i_SET=sr_set,
  15         i_CLR=sr_clr,
  16         o_Q=q)
  17 print(rtlil.convert(m, ports=[sr_set, sr_clr, q]))