1 from nmigen
import Signal
, Const
2 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
3 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
9 def __init__(self
, pspec
):
10 self
.ctx
= FPPipeContext(pspec
)
11 self
.muxid
= self
.ctx
.muxid
17 return [self
.ctx
.eq(i
.ctx
)]
20 return self
.ctx
.ports()
23 class ALUInputData(IntegerData
):
24 def __init__(self
, pspec
):
25 super().__init
__(pspec
)
26 self
.a
= Signal(64, reset_less
=True) # RA
27 self
.b
= Signal(64, reset_less
=True) # RB/immediate
28 self
.so
= Signal(reset_less
=True)
29 self
.carry_in
= Signal(reset_less
=True)
32 yield from super().__iter
__()
40 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
41 self
.carry_in
.eq(i
.carry_in
),
44 # TODO: ALUIntermediateData which does not have
45 # cr0, ov, ov32 in it (because they are generated as outputs by
46 # the final output stage, not by the intermediate stage)
47 # https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
49 class ALUOutputData(IntegerData
):
50 def __init__(self
, pspec
):
51 super().__init
__(pspec
)
52 self
.o
= Signal(64, reset_less
=True, name
="stage_o")
53 self
.cr0
= Data(4, name
="cr0")
54 self
.xer_co
= Data(2, name
="xer_co") # bit0: co, bit1: co32
55 self
.xer_ov
= Data(2, name
="xer_ov") # bit0: ov, bit1: ov32
56 self
.xer_so
= Data(1, name
="xer_so")
59 yield from super().__iter
__()
68 return lst
+ [self
.o
.eq(i
.o
),
69 self
.xer_co
.eq(i
.xer_co
),
71 self
.xer_ov
.eq(i
.xer_ov
), self
.xer_so
.eq(i
.xer_so
)]
75 def __init__(self
, id_wid
=2, op_wid
=1):
78 self
.opkls
= lambda _
: CompALUOpSubset(name
="op")
82 class ALUPipeSpec(IntPipeSpec
):
83 def __init__(self
, id_wid
, op_wid
):
84 super().__init
__(id_wid
, op_wid
)
85 self
.pipekls
= SimpleHandshakeRedir