1 from nmigen
import Signal
, Const
2 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
3 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
10 def __init__(self
, pspec
):
11 self
.ctx
= FPPipeContext(pspec
)
12 self
.muxid
= self
.ctx
.muxid
18 return [self
.ctx
.eq(i
.ctx
)]
21 return self
.ctx
.ports()
24 class ALUInputData(IntegerData
):
25 regspec
= [('INT', 'a', '0:63'),
27 ('XER', 'xer_so', '32'),
28 ('XER', 'xer_ca', '34,45')]
29 def __init__(self
, pspec
):
30 super().__init
__(pspec
)
31 self
.a
= Signal(64, reset_less
=True) # RA
32 self
.b
= Signal(64, reset_less
=True) # RB/immediate
33 self
.xer_so
= Signal(reset_less
=True) # XER bit 32: SO
34 self
.xer_ca
= Signal(2, reset_less
=True) # XER bit 34/45: CA/CA32
37 yield from super().__iter
__()
45 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
46 self
.xer_ca
.eq(i
.xer_ca
),
47 self
.xer_so
.eq(i
.xer_so
)]
50 class ALUOutputData(IntegerData
):
51 regspec
= [('INT', 'o', '0:63'),
53 ('XER', 'xer_ca', '34,45'),
54 ('XER', 'xer_ov', '33,44'),
55 ('XER', 'xer_so', '32')]
56 def __init__(self
, pspec
):
57 super().__init
__(pspec
)
58 self
.o
= Signal(64, reset_less
=True, name
="stage_o")
59 self
.cr0
= Data(4, name
="cr0")
60 self
.xer_ca
= Data(2, name
="xer_co") # bit0: ca, bit1: ca32
61 self
.xer_ov
= Data(2, name
="xer_ov") # bit0: ov, bit1: ov32
62 self
.xer_so
= Data(1, name
="xer_so")
65 yield from super().__iter
__()
74 return lst
+ [self
.o
.eq(i
.o
),
75 self
.xer_ca
.eq(i
.xer_ca
),
77 self
.xer_ov
.eq(i
.xer_ov
), self
.xer_so
.eq(i
.xer_so
)]
81 def __init__(self
, id_wid
=2, op_wid
=1):
84 self
.opkls
= lambda _
: CompALUOpSubset(name
="op")
88 class ALUPipeSpec(IntPipeSpec
):
89 regspec
= (ALUInputData
.regspec
, ALUOutputData
.regspec
)
90 def __init__(self
, id_wid
, op_wid
):
91 super().__init
__(id_wid
, op_wid
)
92 self
.pipekls
= SimpleHandshakeRedir