1 from soc
.fu
.test
.common
import (TestAccumulatorBase
, skip_case
)
2 from soc
.config
.endian
import bigendian
3 from soc
.simulator
.program
import Program
4 from soc
.decoder
.isa
.caller
import SVP64State
5 from soc
.sv
.trans
.svp64
import SVP64Asm
8 class SVP64ALUTestCase(TestAccumulatorBase
):
10 def case_1_sv_add(self
):
12 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
13 # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
14 isa
= SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
18 # initial values in GPR regfile
19 initial_regs
= [0] * 32
20 initial_regs
[9] = 0x1234
21 initial_regs
[10] = 0x1111
22 initial_regs
[5] = 0x4321
23 initial_regs
[6] = 0x2223
24 # SVSTATE (in this case, VL=2)
25 svstate
= SVP64State()
26 svstate
.vl
[0:7] = 2 # VL
27 svstate
.maxvl
[0:7] = 2 # MAXVL
28 print("SVSTATE", bin(svstate
.spr
.asint()))
30 self
.add_case(Program(lst
, bigendian
), initial_regs
,
31 initial_svstate
=svstate
)
33 def case_2_sv_add_scalar(self
):
35 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
36 isa
= SVP64Asm(['sv.add 1, 5, 9'])
40 # initial values in GPR regfile
41 initial_regs
= [0] * 32
42 initial_regs
[9] = 0x1234
43 initial_regs
[5] = 0x4321
44 svstate
= SVP64State()
45 # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
46 svstate
.vl
[0:7] = 1 # VL
47 svstate
.maxvl
[0:7] = 1 # MAXVL
48 print("SVSTATE", bin(svstate
.spr
.asint()))
50 self
.add_case(Program(lst
, bigendian
), initial_regs
,
51 initial_svstate
=svstate
)
53 # This case helps checking the encoding of the Extra field
54 # It was built so the v3.0b registers are: 3, 2, 1
55 # and the Extra field is: 101.110.111
56 # The expected SVP64 register numbers are: 13, 10, 7
57 # Any mistake in decoding will probably give a different answer
58 def case_3_sv_check_extra(self
):
60 # 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012
61 isa
= SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
65 # initial values in GPR regfile
66 initial_regs
= [0] * 32
67 initial_regs
[7] = 0x3012
68 initial_regs
[10] = 0x1230
69 svstate
= SVP64State()
70 # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
71 svstate
.vl
[0:7] = 1 # VL
72 svstate
.maxvl
[0:7] = 1 # MAXVL
73 print("SVSTATE", bin(svstate
.spr
.asint()))
75 self
.add_case(Program(lst
, bigendian
), initial_regs
,
76 initial_svstate
=svstate
)
78 def case_4_sv_add_(self
):
79 # adds when Rc=1: TODO CRs higher up
80 # 1 = 5 + 9 => 0 = -1+1 CR0=0b100
81 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
83 isa
= SVP64Asm(['sv.add. 1.v, 5.v, 9.v'])
87 # initial values in GPR regfile
88 initial_regs
= [0] * 32
89 initial_regs
[9] = 0xffffffffffffffff
90 initial_regs
[10] = 0x1111
92 initial_regs
[6] = 0x2223
94 # SVSTATE (in this case, VL=2)
95 svstate
= SVP64State()
96 svstate
.vl
[0:7] = 2 # VL
97 svstate
.maxvl
[0:7] = 2 # MAXVL
98 print("SVSTATE", bin(svstate
.spr
.asint()))
100 self
.add_case(Program(lst
, bigendian
), initial_regs
,
101 initial_svstate
=svstate
)
103 def case_5_sv_check_vl_0(self
):
105 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
107 'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0
111 print("listing", lst
)
113 # initial values in GPR regfile
114 initial_regs
= [0] * 32
115 initial_regs
[9] = 0x1234
116 initial_regs
[5] = 0x4321
117 initial_regs
[7] = 0x3012
118 initial_regs
[10] = 0x1230
119 svstate
= SVP64State()
120 # SVSTATE (in this case, VL=0, so vector instructions are skipped)
121 svstate
.vl
[0:7] = 0 # VL
122 svstate
.maxvl
[0:7] = 0 # MAXVL
123 print("SVSTATE", bin(svstate
.spr
.asint()))
125 self
.add_case(Program(lst
, bigendian
), initial_regs
,
126 initial_svstate
=svstate
)
128 # checks that SRCSTEP was reset properly after an SV instruction
129 def case_6_sv_add_multiple(self
):
131 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
132 # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
133 # 3 = 7 + 11 => 0x4242 = 0x3012 + 0x1230
134 # 13 = 10 + 7 => 0x2341 = 0x1111 + 0x1230
135 # 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000
136 # 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234
138 'sv.add 1.v, 5.v, 9.v',
139 'sv.add 13.v, 10.v, 7.v'
142 print("listing", lst
)
144 # initial values in GPR regfile
145 initial_regs
= [0] * 32
146 initial_regs
[9] = 0x1234
147 initial_regs
[10] = 0x1111
148 initial_regs
[11] = 0x3012
149 initial_regs
[5] = 0x4321
150 initial_regs
[6] = 0x2223
151 initial_regs
[7] = 0x1230
152 # SVSTATE (in this case, VL=3)
153 svstate
= SVP64State()
154 svstate
.vl
[0:7] = 3 # VL
155 svstate
.maxvl
[0:7] = 3 # MAXVL
156 print("SVSTATE", bin(svstate
.spr
.asint()))
158 self
.add_case(Program(lst
, bigendian
), initial_regs
,
159 initial_svstate
=svstate
)
161 def case_7_sv_add_2(self
):
163 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
164 # r1 is scalar so ENDS EARLY
165 isa
= SVP64Asm(['sv.add 1, 5.v, 9.v'])
167 print("listing", lst
)
169 # initial values in GPR regfile
170 initial_regs
= [0] * 32
171 initial_regs
[9] = 0x1234
172 initial_regs
[10] = 0x1111
173 initial_regs
[5] = 0x4321
174 initial_regs
[6] = 0x2223
175 # SVSTATE (in this case, VL=2)
176 svstate
= SVP64State()
177 svstate
.vl
[0:7] = 2 # VL
178 svstate
.maxvl
[0:7] = 2 # MAXVL
179 print("SVSTATE", bin(svstate
.spr
.asint()))
180 self
.add_case(Program(lst
, bigendian
), initial_regs
,
181 initial_svstate
=svstate
)
183 def case_8_sv_add_3(self
):
185 # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
186 # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
187 isa
= SVP64Asm(['sv.add 1.v, 5, 9.v'])
189 print("listing", lst
)
191 # initial values in GPR regfile
192 initial_regs
= [0] * 32
193 initial_regs
[9] = 0x1234
194 initial_regs
[10] = 0x1111
195 initial_regs
[5] = 0x4321
196 initial_regs
[6] = 0x2223
197 # SVSTATE (in this case, VL=2)
198 svstate
= SVP64State()
199 svstate
.vl
[0:7] = 2 # VL
200 svstate
.maxvl
[0:7] = 2 # MAXVL
201 print("SVSTATE", bin(svstate
.spr
.asint()))
202 self
.add_case(Program(lst
, bigendian
), initial_regs
,
203 initial_svstate
=svstate
)