1 # This stage is intended to handle the gating of carry out,
2 # and updating the condition register
3 from nmigen
import (Module
, Signal
, Cat
, Const
)
4 from nmutil
.pipemodbase
import PipeModBase
5 from ieee754
.part
.partsig
import PartitionedSignal
6 from soc
.decoder
.power_enums
import MicrOp
9 class CommonOutputStage(PipeModBase
):
10 def __init__(self
, pspec
):
11 super().__init
__(pspec
, "output")
13 def elaborate(self
, platform
):
17 # ok so there are two different ways this goes:
18 # (1) something involving XER ov in which case so gets modified
19 # and that means we need the modified version of so in CR0
20 # (2) something that does *not* have XER ov, in which case so
21 # has been pass-through just to get it into CR0
22 # in case (1) we don't *have* an xer_so output so put xer_so *input*
24 if hasattr(self
.o
, "xer_so"):
25 xer_so_o
= self
.o
.xer_so
.data
[0]
27 xer_so_o
= self
.i
.xer_so
.data
[0]
29 # op requests inversion of the output...
30 o
= Signal
.like(self
.i
.o
)
31 if hasattr(op
, "invert_out"): # ... optionally
32 with m
.If(op
.invert_out
):
33 comb
+= o
.eq(~self
.i
.o
.data
)
35 comb
+= o
.eq(self
.i
.o
.data
)
37 comb
+= o
.eq(self
.i
.o
.data
) # ... no inversion
39 # target register if 32-bit is only the 32 LSBs
40 # XXX ah. right. this needs to be done only if the *mode* is 32-bit
41 # see https://bugs.libre-soc.org/show_bug.cgi?id=424
42 target
= Signal(64, reset_less
=True)
43 #with m.If(op.is_32bit):
44 # comb += target.eq(o[:32])
46 # comb += target.eq(o)
49 # carry-out only if actually present in this input spec
50 # (note: MUL and DIV do not have it, but ALU and Logical do)
51 if hasattr(self
.i
, "xer_ca"):
53 comb
+= self
.o
.xer_ca
.data
.eq(self
.i
.xer_ca
.data
)
54 comb
+= self
.o
.xer_ca
.ok
.eq(op
.output_carry
)
56 # create condition register cr0 and sticky-overflow
57 is_nzero
= Signal(reset_less
=True)
58 is_positive
= Signal(reset_less
=True)
59 is_negative
= Signal(reset_less
=True)
60 msb_test
= Signal(reset_less
=True) # set equal to MSB, invert if OP=CMP
61 is_cmp
= Signal(reset_less
=True) # true if OP=CMP
62 is_cmpeqb
= Signal(reset_less
=True) # true if OP=CMPEQB
63 cr0
= Signal(4, reset_less
=True)
65 # TODO: if o[63] is XORed with "operand == OP_CMP"
66 # that can be used as a test of whether to invert the +ve/-ve test
67 # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
69 comb
+= is_cmp
.eq(op
.insn_type
== MicrOp
.OP_CMP
)
70 comb
+= is_cmpeqb
.eq(op
.insn_type
== MicrOp
.OP_CMPEQB
)
71 # nope - if *processor* mode is 32-bit
72 #with m.If(op.is_32bit):
73 # comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
75 # comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
76 comb
+= msb_test
.eq(target
[-1]) # 64-bit MSB
77 comb
+= is_nzero
.eq(target
.bool())
78 with m
.If(is_cmp
): # invert pos/neg tests
79 comb
+= is_positive
.eq(msb_test
)
80 comb
+= is_negative
.eq(is_nzero
& ~msb_test
)
82 comb
+= is_negative
.eq(msb_test
)
83 comb
+= is_positive
.eq(is_nzero
& ~msb_test
)
86 comb
+= cr0
.eq(self
.i
.cr0
.data
)
88 comb
+= cr0
.eq(Cat(xer_so_o
, ~is_nzero
, is_positive
, is_negative
))
90 # copy out [inverted?] output, cr0, and context out
91 comb
+= self
.o
.o
.data
.eq(o
)
92 comb
+= self
.o
.o
.ok
.eq(self
.i
.o
.ok
)
94 comb
+= self
.o
.cr0
.data
.eq(cr0
)
95 comb
+= self
.o
.cr0
.ok
.eq(op
.write_cr0
)
97 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)