src/soc/fu/common_output_stage.py

   1 # This stage is intended to handle the gating of carry out,
   2 # and updating the condition register
   3 from nmigen import (Module, Signal, Cat, Const)
   4 from nmutil.pipemodbase import PipeModBase
   5 from ieee754.part.partsig import SimdSignal
   6 from openpower.decoder.power_enums import MicrOp
   7
   8
   9 class CommonOutputStage(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "output")
  12
  13     def elaborate(self, platform):
  14         XLEN = self.pspec.XLEN
  15         m = Module()
  16         comb = m.d.comb
  17         op = self.i.ctx.op
  18         # ok so there are two different ways this goes:
  19         # (1) something involving XER ov in which case so gets modified
  20         #     and that means we need the modified version of so in CR0
  21         # (2) something that does *not* have XER ov, in which case so
  22         #     has been pass-through just to get it into CR0
  23         # in case (1) we don't *have* an xer_so output so put xer_so *input*
  24         # into CR0.
  25         xer_so_i = self.i.xer_so.data[0]
  26         if hasattr(self.o, "xer_so"):
  27             xer_so_o = self.o.xer_so.data[0]
  28             so = Signal(reset_less=True)
  29             oe = Signal(reset_less=True)
  30             comb += oe.eq(op.oe.oe & op.oe.ok)
  31             with m.If(oe):
  32                 comb += so.eq(xer_so_o)
  33             with m.Else():
  34                 comb += so.eq(xer_so_i)
  35         else:
  36             so = xer_so_i
  37
  38         with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
  39             # op requests inversion of the output...
  40             o = Signal.like(self.i.o)
  41             if hasattr(op, "invert_out"): # ... optionally
  42                 with m.If(op.invert_out):
  43                     comb += o.eq(~self.i.o.data)
  44                 with m.Else():
  45                     comb += o.eq(self.i.o.data)
  46             else:
  47                 comb += o.eq(self.i.o.data) # ... no inversion
  48
  49         # target register if 32-bit is only the 32 LSBs
  50         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
  51         # (an MSR bit)
  52         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
  53         target = Signal(XLEN, reset_less=True)
  54         #with m.If(op.is_32bit):
  55         #    comb += target.eq(o[:32])
  56         #with m.Else():
  57         #    comb += target.eq(o)
  58         comb += target.eq(o)
  59
  60         # carry-out only if actually present in this input spec
  61         # (note: MUL and DIV do not have it, but ALU and Logical do)
  62         if hasattr(self.i, "xer_ca"):
  63             # Handle carry_out
  64             comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
  65             comb += self.o.xer_ca.ok.eq(op.output_carry)
  66
  67         # create condition register cr0 and sticky-overflow
  68         is_nzero = Signal(reset_less=True)
  69         is_positive = Signal(reset_less=True)
  70         is_negative = Signal(reset_less=True)
  71         msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
  72         is_cmp = Signal(reset_less=True)     # true if OP=CMP
  73         is_cmpeqb = Signal(reset_less=True)  # true if OP=CMPEQB
  74         cr0 = Signal(4, reset_less=True)
  75
  76         # TODO: if o[63] is XORed with "operand == OP_CMP"
  77         # that can be used as a test of whether to invert the +ve/-ve test
  78         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
  79
  80         comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
  81         comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
  82
  83         comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
  84         comb += is_nzero.eq(target.bool())
  85         comb += is_negative.eq(msb_test)
  86         comb += is_positive.eq(is_nzero & ~msb_test)
  87
  88         with m.If(is_cmpeqb | is_cmp):
  89             comb += cr0.eq(self.i.cr0.data)
  90         with m.Else():
  91             comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
  92
  93         # copy out [inverted?] output, cr0, and context out
  94         comb += self.o.o.data.eq(o)
  95         comb += self.o.o.ok.eq(self.i.o.ok)
  96         comb += self.o.cr0.data.eq(cr0) # CR0 to be set
  97         comb += self.o.cr0.ok.eq(op.write_cr0)
  98         comb += self.o.ctx.eq(self.i.ctx) # context
  99
 100         return m