src/soc/fu/compunits/test/test_shiftrot_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
   6 from soc.fu.shift_rot.test.test_pipe_caller import test_data
   7
   8 from soc.fu.compunits.compunits import ShiftRotFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11 from soc.decoder.power_enums import CryIn
  12
  13
  14 class ShiftRotTestRunner(TestRunner):
  15     def __init__(self, test_data):
  16         super().__init__(test_data, ShiftRotFunctionUnit, self,
  17                          Function.SHIFT_ROT)
  18
  19     def get_cu_inputs(self, dec2, sim):
  20         """naming (res) must conform to ShiftRotFunctionUnit input regspec
  21         """
  22         res = {}
  23
  24         # RA
  25         reg1_ok = yield dec2.e.read_reg1.ok
  26         if reg1_ok:
  27             data1 = yield dec2.e.read_reg1.data
  28             res['ra'] = sim.gpr(data1).value
  29
  30         # RB
  31         reg2_ok = yield dec2.e.read_reg2.ok
  32         if reg2_ok:
  33             data2 = yield dec2.e.read_reg2.data
  34             res['rb'] = sim.gpr(data2).value
  35
  36         # RS (RC)
  37         reg3_ok = yield dec2.e.read_reg3.ok
  38         if reg3_ok:
  39             data3 = yield dec2.e.read_reg3.data
  40             res['rc'] = sim.gpr(data3).value
  41
  42         # XER.ca
  43         cry_in = yield dec2.e.input_carry
  44         if cry_in == CryIn.CA.value:
  45             carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  46             carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  47             res['xer_ca'] = carry | (carry32<<1)
  48
  49         print ("inputs", res)
  50
  51         return res
  52
  53     def check_cu_outputs(self, res, dec2, sim, code):
  54         """naming (res) must conform to ShiftRotFunctionUnit output regspec
  55         """
  56
  57         print ("outputs", repr(code), res)
  58
  59         # RT
  60         out_reg_valid = yield dec2.e.write_reg.ok
  61         if out_reg_valid:
  62             write_reg_idx = yield dec2.e.write_reg.data
  63             expected = sim.gpr(write_reg_idx).value
  64             cu_out = res['o']
  65             print(f"expected {expected:x}, actual: {cu_out:x}")
  66             self.assertEqual(expected, cu_out, code)
  67
  68         rc = yield dec2.e.rc.data
  69         op = yield dec2.e.insn_type
  70         cridx_ok = yield dec2.e.write_cr.ok
  71         cridx = yield dec2.e.write_cr.data
  72
  73         print ("check extra output", repr(code), cridx_ok, cridx)
  74
  75         if rc:
  76             self.assertEqual(cridx_ok, 1, code)
  77             self.assertEqual(cridx, 0, code)
  78
  79         # CR (CR0-7)
  80         if cridx_ok:
  81             cr_expected = sim.crl[cridx].get_range().value
  82             cr_actual = res['cr_a']
  83             print ("CR", cridx, cr_expected, cr_actual)
  84             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  85
  86         # XER.ca
  87         cry_out = yield dec2.e.output_carry
  88         if cry_out:
  89             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  90             xer_ca = res['xer_ca']
  91             real_carry = xer_ca & 0b1 # XXX CO not CO32
  92             self.assertEqual(expected_carry, real_carry, code)
  93             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  94             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  95             self.assertEqual(expected_carry32, real_carry32, code)
  96
  97
  98 if __name__ == "__main__":
  99     unittest.main(exit=False)
 100     suite = unittest.TestSuite()
 101     suite.addTest(ShiftRotTestRunner(test_data))
 102
 103     runner = unittest.TextTestRunner()
 104     runner.run(suite)