src/soc/fu/cr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import TestCase
  16 from soc.fu.cr.pipeline import CRBasePipe
  17 from soc.fu.cr.pipe_data import CRPipeSpec
  18 import random
  19
  20
  21
  22 # This test bench is a bit different than is usual. Initially when I
  23 # was writing it, I had all of the tests call a function to create a
  24 # device under test and simulator, initialize the dut, run the
  25 # simulation for ~2 cycles, and assert that the dut output what it
  26 # should have. However, this was really slow, since it needed to
  27 # create and tear down the dut and simulator for every test case.
  28
  29 # Now, instead of doing that, every test case in ALUTestCase puts some
  30 # data into the test_data list below, describing the instructions to
  31 # be tested and the initial state. Once all the tests have been run,
  32 # test_data gets passed to TestRunner which then sets up the DUT and
  33 # simulator once, runs all the data through it, and asserts that the
  34 # results match the pseudocode sim at every cycle.
  35
  36 # By doing this, I've reduced the time it takes to run the test suite
  37 # massively. Before, it took around 1 minute on my computer, now it
  38 # takes around 3 seconds
  39
  40 test_data = []
  41
  42
  43 class CRTestCase(FHDLTestCase):
  44     def __init__(self, name):
  45         super().__init__(name)
  46         self.test_name = name
  47
  48     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  49                         initial_cr=0):
  50         tc = TestCase(prog, self.test_name,
  51                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr)
  52         test_data.append(tc)
  53
  54     def test_crop(self):
  55         insns = ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
  56                  "crandc", "crorc"]
  57         for i in range(40):
  58             choice = random.choice(insns)
  59             ba = random.randint(0, 31)
  60             bb = random.randint(0, 31)
  61             bt = random.randint(0, 31)
  62             lst = [f"{choice} {ba}, {bb}, {bt}"]
  63             cr = random.randint(0, (1<<32)-1)
  64             self.run_tst_program(Program(lst), initial_cr=cr)
  65
  66     def test_crand(self):
  67         for i in range(20):
  68             lst = ["crand 0, 11, 13"]
  69             cr = random.randint(0, (1<<32)-1)
  70             self.run_tst_program(Program(lst), initial_cr=cr)
  71
  72     def test_mcrf(self):
  73         lst = ["mcrf 5, 1"]
  74         cr = 0xfeff0000
  75         self.run_tst_program(Program(lst), initial_cr=cr)
  76
  77     def test_mtcrf(self):
  78         for i in range(20):
  79             mask = random.randint(0, 255)
  80             lst = [f"mtcrf {mask}, 2"]
  81             cr = random.randint(0, (1<<32)-1)
  82             initial_regs = [0] * 32
  83             initial_regs[2] = random.randint(0, (1<<32)-1)
  84             self.run_tst_program(Program(lst), initial_regs=initial_regs,
  85                                  initial_cr=cr)
  86     def test_mtocrf(self):
  87         for i in range(20):
  88             mask = 1<<random.randint(0, 7)
  89             lst = [f"mtocrf {mask}, 2"]
  90             cr = random.randint(0, (1<<32)-1)
  91             initial_regs = [0] * 32
  92             initial_regs[2] = random.randint(0, (1<<32)-1)
  93             self.run_tst_program(Program(lst), initial_regs=initial_regs,
  94                                  initial_cr=cr)
  95
  96     def test_mfcr(self):
  97         for i in range(5):
  98             lst = ["mfcr 2"]
  99             cr = random.randint(0, (1<<32)-1)
 100             self.run_tst_program(Program(lst), initial_cr=cr)
 101
 102     def test_mfocrf(self):
 103         for i in range(20):
 104             mask = 1<<random.randint(0, 7)
 105             lst = [f"mfocrf 2, {mask}"]
 106             cr = random.randint(0, (1<<32)-1)
 107             self.run_tst_program(Program(lst), initial_cr=cr)
 108
 109     def test_isel(self):
 110         for i in range(20):
 111             bc = random.randint(0, 31)
 112             lst = [f"isel 1, 2, 3, {bc}"]
 113             cr = random.randint(0, (1<<32)-1)
 114             initial_regs = [0] * 32
 115             initial_regs[2] = random.randint(0, (1<<64)-1)
 116             initial_regs[3] = random.randint(0, (1<<64)-1)
 117             self.run_tst_program(Program(lst),
 118                                  initial_regs=initial_regs, initial_cr=cr)
 119
 120     def test_setb(self):
 121         for i in range(20):
 122             bfa = random.randint(0, 7)
 123             lst = [f"setb 1, {bfa}"]
 124             cr = random.randint(0, (1<<32)-1)
 125             self.run_tst_program(Program(lst), initial_cr=cr)
 126
 127
 128
 129     def test_ilang(self):
 130         pspec = CRPipeSpec(id_wid=2)
 131         alu = CRBasePipe(pspec)
 132         vl = rtlil.convert(alu, ports=alu.ports())
 133         with open("cr_pipeline.il", "w") as f:
 134             f.write(vl)
 135
 136
 137 def get_cu_inputs(dec2, sim):
 138     """naming (res) must conform to CRFunctionUnit input regspec
 139     """
 140     res = {}
 141     full_reg = yield dec2.e.read_cr_whole
 142
 143     # full CR
 144     print(sim.cr.get_range().value)
 145     if full_reg:
 146         res['full_cr'] = sim.cr.get_range().value
 147     else:
 148         # CR A
 149         cr1_en = yield dec2.e.read_cr1.ok
 150         if cr1_en:
 151             cr1_sel = yield dec2.e.read_cr1.data
 152             res['cr_a'] = sim.crl[cr1_sel].get_range().value
 153         cr2_en = yield dec2.e.read_cr2.ok
 154         # CR B
 155         if cr2_en:
 156             cr2_sel = yield dec2.e.read_cr2.data
 157             res['cr_b'] = sim.crl[cr2_sel].get_range().value
 158         cr3_en = yield dec2.e.read_cr3.ok
 159         # CR C
 160         if cr3_en:
 161             cr3_sel = yield dec2.e.read_cr3.data
 162             res['cr_c'] = sim.crl[cr3_sel].get_range().value
 163
 164     # RA/RC
 165     reg1_ok = yield dec2.e.read_reg1.ok
 166     if reg1_ok:
 167         data1 = yield dec2.e.read_reg1.data
 168         res['ra'] = sim.gpr(data1).value
 169
 170     # RB (or immediate)
 171     reg2_ok = yield dec2.e.read_reg2.ok
 172     if reg2_ok:
 173         data2 = yield dec2.e.read_reg2.data
 174         res['rb'] = sim.gpr(data2).value
 175
 176     print ("get inputs", res)
 177     return res
 178
 179
 180 class TestRunner(FHDLTestCase):
 181     def __init__(self, test_data):
 182         super().__init__("run_all")
 183         self.test_data = test_data
 184
 185     def set_inputs(self, alu, dec2, simulator):
 186         inp = yield from get_cu_inputs(dec2, simulator)
 187         if 'full_cr' in inp:
 188             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 189         else:
 190             yield alu.p.data_i.full_cr.eq(0)
 191         if 'cr_a' in inp:
 192             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 193         if 'cr_b' in inp:
 194             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 195         if 'cr_c' in inp:
 196             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 197         if 'ra' in inp:
 198             yield alu.p.data_i.ra.eq(inp['ra'])
 199         else:
 200             yield alu.p.data_i.ra.eq(0)
 201         if 'rb' in inp:
 202             yield alu.p.data_i.rb.eq(inp['rb'])
 203         else:
 204             yield alu.p.data_i.rb.eq(0)
 205
 206     def assert_outputs(self, alu, dec2, simulator, code):
 207         whole_reg = yield dec2.e.write_cr_whole
 208         cr_en = yield dec2.e.write_cr.ok
 209         if whole_reg:
 210             full_cr = yield alu.n.data_o.full_cr.data
 211             expected_cr = simulator.cr.get_range().value
 212             self.assertEqual(expected_cr, full_cr, code)
 213         elif cr_en:
 214             cr_sel = yield dec2.e.write_cr.data
 215             expected_cr = simulator.crl[cr_sel].get_range().value
 216             real_cr = yield alu.n.data_o.cr.data
 217             self.assertEqual(expected_cr, real_cr, code)
 218         alu_out = yield alu.n.data_o.o.data
 219         out_reg_valid = yield dec2.e.write_reg.ok
 220         if out_reg_valid:
 221             write_reg_idx = yield dec2.e.write_reg.data
 222             expected = simulator.gpr(write_reg_idx).value
 223             print(f"expected {expected:x}, actual: {alu_out:x}")
 224             self.assertEqual(expected, alu_out, code)
 225
 226     def run_all(self):
 227         m = Module()
 228         comb = m.d.comb
 229         instruction = Signal(32)
 230
 231         pdecode = create_pdecode()
 232
 233         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 234
 235         pspec = CRPipeSpec(id_wid=2)
 236         m.submodules.alu = alu = CRBasePipe(pspec)
 237
 238         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 239         comb += alu.n.ready_i.eq(1)
 240         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 241         sim = Simulator(m)
 242
 243         sim.add_clock(1e-6)
 244         def process():
 245             for test in self.test_data:
 246                 print(test.name)
 247                 program = test.program
 248                 self.subTest(test.name)
 249                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
 250                 gen = program.generate_instructions()
 251                 instructions = list(zip(gen, program.assembly.splitlines()))
 252
 253                 index = sim.pc.CIA.value//4
 254                 while index < len(instructions):
 255                     ins, code = instructions[index]
 256
 257                     print("0x{:X}".format(ins & 0xffffffff))
 258                     print(code)
 259
 260                     # ask the decoder to decode this binary data (endian'd)
 261                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 262                     yield instruction.eq(ins)          # raw binary instr.
 263                     yield Settle()
 264                     yield from self.set_inputs(alu, pdecode2, sim)
 265                     yield alu.p.valid_i.eq(1)
 266                     fn_unit = yield pdecode2.e.fn_unit
 267                     self.assertEqual(fn_unit, Function.CR.value, code)
 268                     yield
 269                     opname = code.split(' ')[0]
 270                     yield from sim.call(opname)
 271                     index = sim.pc.CIA.value//4
 272
 273                     vld = yield alu.n.valid_o
 274                     while not vld:
 275                         yield
 276                         vld = yield alu.n.valid_o
 277                     yield
 278                     yield from self.assert_outputs(alu, pdecode2, sim, code)
 279
 280         sim.add_sync_process(process)
 281         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 282                             traces=[]):
 283             sim.run()
 284
 285
 286 if __name__ == "__main__":
 287     unittest.main(exit=False)
 288     suite = unittest.TestSuite()
 289     suite.addTest(TestRunner(test_data))
 290
 291     runner = unittest.TextTestRunner()
 292     runner.run(suite)