1 from nmigen
import Signal
, Const
2 from soc
.fu
.alu
.alu_input_record
import CompLDSTOpSubset
3 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
8 class LDSTInputData(IntegerData
):
9 regspec
= [('INT', 'ra', '0:63'), # RA
10 ('INT', 'rb', '0:63'), # RB/immediate
11 ('INT', 'rc', '0:63'), # RC
12 ('XER', 'xer_so', '32')] # XER bit 32: SO
14 def __init__(self
, pspec
):
15 super().__init
__(pspec
, False)
20 class LDSTOutputData(IntegerData
):
21 regspec
= [('INT', 'o', '0:63'), # RT
22 ('INT', 'o1', '0:63'), # RA (effective address, update mode)
23 ('CR', 'cr_a', '0:3'),
24 ('XER', 'xer_so', '32')]
25 def __init__(self
, pspec
):
26 super().__init
__(pspec
, True)
28 self
.cr0
, self
.ea
= self
.cr_a
, self
.o1
31 class LDSTPipeSpec(CommonPipeSpec
):
32 regspec
= (LDSTInputData
.regspec
, LDSTOutputData
.regspec
)
33 opsubsetkls
= CompLDSTOpSubset