Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / ldst / test / test_pipe_caller.py
1 from openpower.decoder.power_enums import XER_bits
2 from openpower.test.ldst.ldst_cases import LDSTTestCase
3
4 def get_cu_inputs(dec2, sim):
5 """naming (res) must conform to LDSTFunctionUnit input regspec
6 """
7 res = {}
8
9 # RA
10 reg1_ok = yield dec2.e.read_reg1.ok
11 if reg1_ok:
12 data1 = yield dec2.e.read_reg1.data
13 res['ra'] = sim.gpr(data1).value
14
15 # RB (or immediate)
16 reg2_ok = yield dec2.e.read_reg2.ok
17 if reg2_ok:
18 data2 = yield dec2.e.read_reg2.data
19 res['rb'] = sim.gpr(data2).value
20
21 # RC
22 reg3_ok = yield dec2.e.read_reg3.ok
23 if reg3_ok:
24 data3 = yield dec2.e.read_reg3.data
25 res['rc'] = sim.gpr(data3).value
26
27 # XER.so
28 oe = yield dec2.e.do.oe.data[0] & dec2.e.do.oe.ok
29 if oe:
30 so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
31 res['xer_so'] = so
32
33 return res
34
35