src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.logical.pipeline import LogicalBasePipe
  15 from soc.fu.logical.pipe_data import LogicalPipeSpec
  16 import random
  17
  18
  19 class TestCase:
  20     def __init__(self, program, regs, sprs, name):
  21         self.program = program
  22         self.regs = regs
  23         self.sprs = sprs
  24         self.name = name
  25
  26 def get_cu_inputs(dec2, sim):
  27     """naming (res) must conform to LogicalFunctionUnit input regspec
  28     """
  29     res = {}
  30
  31     # RA (or RC)
  32     reg1_ok = yield dec2.e.read_reg1.ok
  33     if reg1_ok:
  34         data1 = yield dec2.e.read_reg1.data
  35         res['ra'] = sim.gpr(data1).value
  36
  37     # RB (or immediate)
  38     reg2_ok = yield dec2.e.read_reg2.ok
  39     #imm_ok = yield dec2.e.imm_data.imm_ok
  40     if reg2_ok:
  41         data2 = yield dec2.e.read_reg2.data
  42         data2 = sim.gpr(data2).value
  43         res['rb'] = data2
  44     #elif imm_ok:
  45     #    data2 = yield dec2.e.imm_data.imm
  46     #    res['rb'] = data2
  47
  48     return res
  49
  50
  51 def set_alu_inputs(alu, dec2, sim):
  52     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  53     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  54     # and place it into data_i.b
  55
  56     inp = yield from get_cu_inputs(dec2, sim)
  57     if 'ra' in inp:
  58         yield alu.p.data_i.a.eq(inp['ra'])
  59     if 'rb' in inp:
  60         yield alu.p.data_i.b.eq(inp['rb'])
  61     imm_ok = yield dec2.e.imm_data.imm_ok
  62     if imm_ok:
  63         data2 = yield dec2.e.imm_data.imm
  64         yield alu.p.data_i.b.eq(data2)
  65
  66
  67 # This test bench is a bit different than is usual. Initially when I
  68 # was writing it, I had all of the tests call a function to create a
  69 # device under test and simulator, initialize the dut, run the
  70 # simulation for ~2 cycles, and assert that the dut output what it
  71 # should have. However, this was really slow, since it needed to
  72 # create and tear down the dut and simulator for every test case.
  73
  74 # Now, instead of doing that, every test case in ALUTestCase puts some
  75 # data into the test_data list below, describing the instructions to
  76 # be tested and the initial state. Once all the tests have been run,
  77 # test_data gets passed to TestRunner which then sets up the DUT and
  78 # simulator once, runs all the data through it, and asserts that the
  79 # results match the pseudocode sim at every cycle.
  80
  81 # By doing this, I've reduced the time it takes to run the test suite
  82 # massively. Before, it took around 1 minute on my computer, now it
  83 # takes around 3 seconds
  84
  85
  86 class LogicalTestCase(FHDLTestCase):
  87     test_data = []
  88     def __init__(self, name):
  89         super().__init__(name)
  90         self.test_name = name
  91
  92     def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
  93         tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
  94         self.test_data.append(tc)
  95
  96     def test_rand(self):
  97         insns = ["and", "or", "xor"]
  98         for i in range(40):
  99             choice = random.choice(insns)
 100             lst = [f"{choice} 3, 1, 2"]
 101             initial_regs = [0] * 32
 102             initial_regs[1] = random.randint(0, (1 << 64)-1)
 103             initial_regs[2] = random.randint(0, (1 << 64)-1)
 104             self.run_tst_program(Program(lst), initial_regs)
 105
 106     def test_rand_imm_logical(self):
 107         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 108         for i in range(10):
 109             choice = random.choice(insns)
 110             imm = random.randint(0, (1 << 16)-1)
 111             lst = [f"{choice} 3, 1, {imm}"]
 112             print(lst)
 113             initial_regs = [0] * 32
 114             initial_regs[1] = random.randint(0, (1 << 64)-1)
 115             self.run_tst_program(Program(lst), initial_regs)
 116
 117     def test_cntz(self):
 118         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 119         for i in range(100):
 120             choice = random.choice(insns)
 121             lst = [f"{choice} 3, 1"]
 122             print(lst)
 123             initial_regs = [0] * 32
 124             initial_regs[1] = random.randint(0, (1 << 64)-1)
 125             self.run_tst_program(Program(lst), initial_regs)
 126
 127     def test_parity(self):
 128         insns = ["prtyw", "prtyd"]
 129         for i in range(10):
 130             choice = random.choice(insns)
 131             lst = [f"{choice} 3, 1"]
 132             print(lst)
 133             initial_regs = [0] * 32
 134             initial_regs[1] = random.randint(0, (1 << 64)-1)
 135             self.run_tst_program(Program(lst), initial_regs)
 136
 137     def test_popcnt(self):
 138         insns = ["popcntb", "popcntw", "popcntd"]
 139         for i in range(10):
 140             choice = random.choice(insns)
 141             lst = [f"{choice} 3, 1"]
 142             print(lst)
 143             initial_regs = [0] * 32
 144             initial_regs[1] = random.randint(0, (1 << 64)-1)
 145             self.run_tst_program(Program(lst), initial_regs)
 146
 147     def test_popcnt_edge(self):
 148         insns = ["popcntb", "popcntw", "popcntd"]
 149         for choice in insns:
 150             lst = [f"{choice} 3, 1"]
 151             initial_regs = [0] * 32
 152             initial_regs[1] = -1
 153             self.run_tst_program(Program(lst), initial_regs)
 154
 155     def test_cmpb(self):
 156         lst = ["cmpb 3, 1, 2"]
 157         initial_regs = [0] * 32
 158         initial_regs[1] = 0xdeadbeefcafec0de
 159         initial_regs[2] = 0xd0adb0000afec1de
 160         self.run_tst_program(Program(lst), initial_regs)
 161
 162     def test_bpermd(self):
 163         lst = ["bpermd 3, 1, 2"]
 164         for i in range(20):
 165             initial_regs = [0] * 32
 166             initial_regs[1] = 1<<random.randint(0,63)
 167             initial_regs[2] = 0xdeadbeefcafec0de
 168             self.run_tst_program(Program(lst), initial_regs)
 169
 170     def test_ilang(self):
 171         pspec = LogicalPipeSpec(id_wid=2)
 172         alu = LogicalBasePipe(pspec)
 173         vl = rtlil.convert(alu, ports=alu.ports())
 174         with open("logical_pipeline.il", "w") as f:
 175             f.write(vl)
 176
 177
 178 class TestRunner(FHDLTestCase):
 179     def __init__(self, test_data):
 180         super().__init__("run_all")
 181         self.test_data = test_data
 182
 183     def run_all(self):
 184         m = Module()
 185         comb = m.d.comb
 186         instruction = Signal(32)
 187
 188         pdecode = create_pdecode()
 189
 190         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 191
 192         pspec = LogicalPipeSpec(id_wid=2)
 193         m.submodules.alu = alu = LogicalBasePipe(pspec)
 194
 195         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 196         comb += alu.p.valid_i.eq(1)
 197         comb += alu.n.ready_i.eq(1)
 198         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 199         sim = Simulator(m)
 200
 201         sim.add_clock(1e-6)
 202
 203         def process():
 204             for test in self.test_data:
 205                 print(test.name)
 206                 program = test.program
 207                 self.subTest(test.name)
 208                 simulator = ISA(pdecode2, test.regs, test.sprs, 0)
 209                 gen = program.generate_instructions()
 210                 instructions = list(zip(gen, program.assembly.splitlines()))
 211
 212                 index = simulator.pc.CIA.value//4
 213                 while index < len(instructions):
 214                     ins, code = instructions[index]
 215
 216                     print("0x{:X}".format(ins & 0xffffffff))
 217                     print(code)
 218
 219                     # ask the decoder to decode this binary data (endian'd)
 220                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 221                     yield instruction.eq(ins)          # raw binary instr.
 222                     yield Settle()
 223                     fn_unit = yield pdecode2.e.fn_unit
 224                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 225                     yield from set_alu_inputs(alu, pdecode2, simulator)
 226                     yield
 227                     opname = code.split(' ')[0]
 228                     yield from simulator.call(opname)
 229                     index = simulator.pc.CIA.value//4
 230
 231                     vld = yield alu.n.valid_o
 232                     while not vld:
 233                         yield
 234                         vld = yield alu.n.valid_o
 235                     yield
 236                     alu_out = yield alu.n.data_o.o.data
 237                     out_reg_valid = yield pdecode2.e.write_reg.ok
 238                     if out_reg_valid:
 239                         write_reg_idx = yield pdecode2.e.write_reg.data
 240                         expected = simulator.gpr(write_reg_idx).value
 241                         print(f"expected {expected:x}, actual: {alu_out:x}")
 242                         self.assertEqual(expected, alu_out, code)
 243                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 244                                                             simulator, code)
 245
 246         sim.add_sync_process(process)
 247         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 248                            traces=[]):
 249             sim.run()
 250
 251     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 252         rc = yield dec2.e.rc.data
 253         if rc:
 254             cr_expected = sim.crl[0].get_range().value
 255             cr_actual = yield alu.n.data_o.cr0.data
 256             self.assertEqual(cr_expected, cr_actual, code)
 257
 258
 259 if __name__ == "__main__":
 260     unittest.main(exit=False)
 261     suite = unittest.TestSuite()
 262     suite.addTest(TestRunner(LogicalTestCase.test_data))
 263
 264     runner = unittest.TextTestRunner()
 265     runner.run(suite)